Noise resistant semiconductor power module

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

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257700, 257724, 257660, H01L 2312, H01L 2352, H01L 25065

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active

054442974

ABSTRACT:
In a circuit board having four-layered conductive pattern on which a control circuit is arranged, wiring sub-patterns 133a in the first layer are divided into four areas A1-A3 and A8, for respective sets of circuit parts having same power potentials. Respective sub-patterns belonging to the areas A1-A3 are partially or fully surrounded by wiring sub-patterns PEa1 PEa3 connected to negative power potentials of circuit parts belonging to respective areas, respectively. Similarly, at least part of a wiring patten Pa2 for transmitting an input signal to a semiconductor active element is surrounded by a wiring pattern PEa4. Penetration of electric noises to the wiring patterns for the control circuit, in particular to the wiring pattern for transmitting the input signal to semiconductor element, is decreased to thereby prevent misoperation due to electric noises.

REFERENCES:
patent: 4965710 (1990-10-01), Pelly et al.
patent: 5043526 (1991-08-01), Nakagawa et al.
patent: 5077595 (1991-12-01), Fukunaga
patent: 5241456 (1993-08-01), Marcinkiewicz et al.
Patent Abstracts of Japan, vol. 14, No. 239, (E-930), May 21, 1990, J P Kokai #02-065240, Mar. 5, 1990.
Shinohe et al, "Isolation Structure Optimization for High Power Reverse Conducting GTO", 1988 IEEE PESC '88 Record, Apr. 1988 pp. 908-914.

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