Noise resistant reset circuit for a phase detector in a phase-lo

Details Noise resistant reset circuit for a phase detector in a phase-lo Noise resistant reset circuit for a phase detector in a phase-lo

1995-06-06

1997-01-21

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327 12, 327198, 327156, 326104, H03K 1920, H03K 500

Patent

active

055962939

ABSTRACT:
A reset circuit for a phase detector in a phase-locked loop is described. A first set of input lines receives a first set of latched signals corresponding to a cycle of a reference signal applied to the phase detector of the phase-locked loop. Reset assertion logic is connected to the first set of input lines and executes a predetermined logic function on the first set of latched signals to generate a reset signal that is applied to an output node. The generated reset signal has a cycle duration corresponding to the reference signal cycle duration. Reset de-assertion logic is connected to the first set of input lines and executes a predetermined logic function on the first set of latched signals to de-assert the generated reset signal after a period of time corresponding to the reference signal cycle duration. Similar processing may be performed in relation to a second set of latched signals corresponding to a cycle of a feedback signal applied to the phase detector of the phase-locked loop. The reset circuit is immune from latch race conditions and spurious latch reset operations associated with latches in prior art phase-locked loop phase detectors.

REFERENCES:
patent: 4739278 (1988-04-01), Des Brisay, Jr. et al.
patent: 5191239 (1993-03-01), Rogers

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