Noise rejection Set-Reset Flip-Flop circuitry

Details Noise rejection Set-Reset Flip-Flop circuitry Noise rejection Set-Reset Flip-Flop circuitry

1982-06-30

1985-03-19

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307279, 307291, 307443, 307481, G11C 1140, H03K 1716, H03K 17693

Patent

active

045061653

ABSTRACT:
Set-Reset Master-Slave Flip-Flop circuitry uses a feedback circuit connected to a circuitry output terminal and to set and reset input terminals to limit the effect of spurious signals such that only signals applied to set and reset terminals which are of the appropriate state at least prior to and during the transition of a clock signal from the low to the high state cause the output terminals of the Flip-Flop to be set to or maintained in preselected levels.

REFERENCES:
patent: 3976949 (1976-08-01), Hepworth et al.
patent: 4300060 (1981-11-01), Yu
patent: 4349753 (1982-09-01), Scavuzzo

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