Coded data generation or conversion – Digital code to digital code converters – Programmable structure
Reexamination Certificate
2003-02-13
2004-11-02
Young, Brian (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Programmable structure
C327S211000
Reexamination Certificate
active
06812869
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to electrical circuits and, more particularly, to programmable input/output buffers along with design techniques and methodologies for noise reduction.
BACKGROUND
Input/output (I/O) circuits are commonly used for transferring data to and from an integrated circuit or other type of electronic device. I/O circuits (also referred to as input/output buffers, receiver/transmitter circuits, or receiver/driver circuits) are often designed to support a specific type of I/O interface standard (e.g., LVDS or HSTL) or one signal level requirement type within an I/O interface standard (e.g., a specific type of LVDS). These I/O interface standards generally address chip-to-chip interfaces, board-to-board interfaces, and box-to-box interfaces for a wide range of existing and emerging applications, such as data packet processing, data bus bridges, and high-speed memory interfacing.
Due to the growing proliferation of I/O interface standards (i.e., agreed principles of standards), it would be useful for an I/O circuit to have added flexibility, such as for example to support more than one I/O interface standard or more than one signal level requirement type within an I/O interface standard. However, providing this flexibility often leads to unwanted signal integrity issues, such as the introduction of an unacceptable level of noise. As a result, there is a need for noise reduction techniques for programmable input/output circuits.
SUMMARY
Systems and methods are disclosed herein for providing programmable input/output buffers and for reducing noise in programmable input/output buffers. For example, in accordance with an embodiment of the present invention, a programmable I/O buffer, which could be utilized for transmitting and receiving information, is utilized to channel (via its I/O pad) an external reference signal onto an internal reference bus. As another example, in accordance with an embodiment of the present invention, a design technique is presented to reduce the amount of noise injected through a programmable pass transistor associated with a programmable I/O buffer. By utilizing design techniques and methods discussed herein, flexible I/O circuits may be implemented having greater functionality and greater immunity to noise than conventional I/O circuits.
More specifically, in accordance with one embodiment of the present invention, an input/output circuit includes an input/output pad; an input buffer, coupled to the input/output pad, adapted to receive information from the input/output pad; an output buffer, coupled to the input/output pad, adapted to transmit information to the input/output pad; a reference bus adapted to programmably couple to the input buffer and the output buffer; and a transmission gate, coupled to the input/output pad and to the reference bus, adapted to selectively provide a signal path from the input/output pad to the reference bus for a reference signal.
In accordance with another embodiment of the present invention, an integrated circuit includes a plurality of input/output pads; a plurality of input/output buffers coupled to a corresponding first number of input/output pads from the plurality of input/output pads; and means for receiving a reference signal from one of the first number of input/output pads and selectively providing the reference signal to the plurality of input/output buffers corresponding to the remaining ones of the first number of input/output pads.
In accordance with another embodiment of the present invention, a method, for providing a reference signal in an input/output circuit bank, includes providing a plurality of input/output signal paths; associating a reference bus with the input/output signal paths; configuring one of the plurality of input/output signal paths to receive a reference signal and provide the reference signal to the reference bus, and coupling the reference bus to remaining ones of the plurality of input/output signal paths that require the reference signal.
The scope of the invention is defined by the claims, which are incorporated into this section by reference. A more complete understanding of embodiments of the present invention will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.
REFERENCES:
patent: 6320441 (2001-11-01), Fletcher et al.
patent: 6339343 (2002-01-01), Kim et al.
LVDS I/O Interface for Gb/s-per-Pin Operation in 0.35-&mgr;m CMOS, by Andrea Boni et al., IEEE Journal of Solid State Circuits, vol. 36, No. 4, Apr. 2001, pp. 706-711.
Rahman Arifur
Scholz Harold
Lattice Semiconductor Corporation
Lauture Joseph
MacPherson Kwok & Chen & Heid LLP
Michelson Greg J.
Young Brian
LandOfFree
Noise reduction techniques for programmable input/output... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Noise reduction techniques for programmable input/output..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Noise reduction techniques for programmable input/output... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3340413