Noise reduction technique for transistors and small devices...

Details Noise reduction technique for transistors and small devices... Noise reduction technique for transistors and small devices...

2008-07-22

2008-07-22

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170

Reexamination Certificate

active

11426082

ABSTRACT:
The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.

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