Noise reduction output buffer

Details Noise reduction output buffer Noise reduction output buffer

1989-10-31

1990-12-18

Wong, Peter S.

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

323315, 323317, 323907, 307304, 3072968, G05F 324

Patent

active

049789058

ABSTRACT:
A circuit for compensating for MOS device response to supply voltage variations, as well as temperature and process variations, in an integrated circuit device. The compensation circuit produces a reference voltage which modulates the gate bias voltage of a MOS transistor such that the gate-to-source bias of the MOS transistor is varied to compensate for variations in the supply voltage as well as for variations in the temperature and manufacturing process. The circuit pulls up the reference voltage toward the supply voltage as the supply increases, thereby increasing the gate drive on the MOS transistor. The circuit provides compensation for both AC and DC supply variations. The MOS transistor is used to modulate the available current sinking capability in an IC device output buffer, such that as the MOS gate drive increases, the current sinking capability is reduced, thereby slowing the output state transitions as the supply increases, and reducing noise caused by supply variations.

REFERENCES:
patent: 4636983 (1987-01-01), Young et al.
patent: 4714901 (1987-12-01), Jain et al.
patent: 4723108 (1988-02-01), Murphy et al.
patent: 4727309 (1988-02-01), Vajdic et al.
patent: 4835487 (1989-05-01), Doyle et al.

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