Noise reduction circuit

Details Noise reduction circuit Noise reduction circuit

2000-12-18

2002-02-26

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C365S189110, C365S205000

Reexamination Certificate

active

06351156

ABSTRACT:

FIELD
The present invention relates to electronic circuits, and more particularly, to a noise reduction circuit.
BACKGROUND
The building blocks of digital systems, such as computers, communication networks, and video information systems, include logic circuits and memory circuits. Logic circuits and memory circuits each have a characteristic delay time. For a logic circuit, the characteristic delay time is the time it takes a logic signal at an input port of the logic circuit to propagate to an output port of the logic circuit. For a memory circuit, the characteristic delay time is the time it takes a bit value in a memory circuit bit cell to propagate to an output port of the memory circuit. One way to build faster and more powerful digital systems is to decrease the circuit delay times of the building blocks.
Logic circuit delay times are decreasing by about 30% with each new generation of circuits in a circuit family. However, memory circuit delay times are not improving at the same rate. For example, the combined bit-line delay and sense amplifier delay in a high performance on-chip cache utilizing differential low-swing sensing is not improving at a 30% rate because the offset voltage of the sense amplifier does not scale. One solution to this problem is to use a single-ended full-swing sense amplifier, which does support voltage scaling.
The bit-line delay in a memory circuit is improved (decreased) by decreasing the threshold voltage of the pass transistors that couple stored data bits to the bit-lines. Decreasing the threshold voltage of a pass transistor in a memory cell decreases the turn-on time of the pass transistor, which decreases the time required to read a bit from a bit-cell. Unfortunately, decreasing the threshold voltage of the pass transistors in a memory also increases the leakage current coupled to the bit-lines in the memory. And when the bit-lines are precharged in preparation for reading a bit-cell, the leakage current in the bit-cells not being read increases the noise on the bit lines. The noise includes white or pink noise and droop on the bit-line during a read operation. Increasing the noise on the bitlines increases the memory read error rate.
For these and other reasons there is a need for the present invention.


REFERENCES:
patent: 5619149 (1997-04-01), Lev et al.
patent: 5850359 (1998-12-01), Liu
patent: 5912838 (1999-06-01), Chevallier
patent: 5943278 (1999-08-01), Su
patent: 6041008 (2000-03-01), Marr
patent: 6061278 (2000-05-01), Kato et al.
patent: 6137319 (2000-10-01), Krishnamurthy et al.
patent: 6198677 (2001-03-01), Hsu et al.

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