Noise reduction circuit

Details Noise reduction circuit Noise reduction circuit

1985-09-17

1987-01-13

Chin, Tommy P.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358 36, H04N 521

Patent

active

046368639

ABSTRACT:
A noise reduction circuit for reducing noise in video signal comprises delay circuits for delaying an output video signal for delay time 2S and H-S (H denotes one horizontal scanning period and S denotes a half of one period of the color subcarrier), an average circuit for averaging the outputs of the delay circuits, a subtraction circuit for subtracting the output of the average circuit from an input video signal, an attenuation circuit for attenuating the output of the subtraction circuit, an addition circuit for adding the output of the attenuation circuit to the input video signal, and an edge detection circuit for detecting the edge of pattern in the input video signal. The attenuation factor of the attenuation circuit is set into zero when the edge of pattern is detected.

REFERENCES:
patent: 4058836 (1977-11-01), Drewery
patent: 4296436 (1981-10-01), Achiha
patent: 4476491 (1984-10-01), Murata
patent: 4539594 (1985-09-01), Illetschko

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