Noise reduction circuit

Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry

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Details

328165, 358167, 358 36, 455306, H04N 5213, H03K 500

Patent

active

049317431

ABSTRACT:
A noise reduction circuit comprises a first circuit for extracting a relatively high frequency component of an input signal and amplitude-limiting a component of said extracted high frequency component exceeding a predetermined level, a second circuit for delaying said input signal such as a video signal by a predetermined time, and a third circuit for adding outputs of said first and second circuits and outputting an added result as an output of said noise reduction circuit.

REFERENCES:
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patent: 3968448 (1976-07-01), Stenning
patent: 3970944 (1976-07-01), Huellwegen
patent: 4559559 (1985-12-01), Hashimoto et al.
patent: 4563704 (1986-01-01), Hirota
patent: 4571613 (1986-02-01), Fukuda
patent: 4646153 (1987-02-01), Fukuda et al.
patent: 4667225 (1987-05-01), Kanda
patent: 4682251 (1987-07-01), Hirota et al.
patent: 4709269 (1987-11-01), Ozaki
Patent Abstract of Japan, vol. 5, No. 30, Abstract of JP-A-55 156 479.
Patent Abstract of Japan, vol. 7, No. 194, Abstract of JP-A-58 96 473.

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