Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry
Patent
1987-07-10
1990-06-05
Miller, Stanley D.
Facsimile and static presentation processing
Facsimile
Specific signal processing circuitry
328165, 358167, 358 36, 455306, H04N 5213, H03K 500
Patent
active
049317431
ABSTRACT:
A noise reduction circuit comprises a first circuit for extracting a relatively high frequency component of an input signal and amplitude-limiting a component of said extracted high frequency component exceeding a predetermined level, a second circuit for delaying said input signal such as a video signal by a predetermined time, and a third circuit for adding outputs of said first and second circuits and outputting an added result as an output of said noise reduction circuit.
REFERENCES:
patent: 3278866 (1966-10-01), Bose
patent: 3968448 (1976-07-01), Stenning
patent: 3970944 (1976-07-01), Huellwegen
patent: 4559559 (1985-12-01), Hashimoto et al.
patent: 4563704 (1986-01-01), Hirota
patent: 4571613 (1986-02-01), Fukuda
patent: 4646153 (1987-02-01), Fukuda et al.
patent: 4667225 (1987-05-01), Kanda
patent: 4682251 (1987-07-01), Hirota et al.
patent: 4709269 (1987-11-01), Ozaki
Patent Abstract of Japan, vol. 5, No. 30, Abstract of JP-A-55 156 479.
Patent Abstract of Japan, vol. 7, No. 194, Abstract of JP-A-58 96 473.
Fujiwara Hisashige
Fukuda Hisatoshi
Callahan Timothy P.
Meller Michael N.
Miller Stanley D.
Victory Company of Japan, Ltd.
LandOfFree
Noise reduction circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Noise reduction circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Noise reduction circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-493855