Noise reduction by linear interpolation using a single sample-an

Details Noise reduction by linear interpolation using a single sample-an Noise reduction by linear interpolation using a single sample-an

1984-07-20

1985-11-26

LaRoche, Eugene R.

Amplifiers

Hum or noise or distortion bucking introduced into signal...

330 51, 328165, 307542, H03F 126

Patent

active

045556695

ABSTRACT:
In a noise reduction circuit, a sample-and-hold circuit operating on a tracking mode is sampled in response to the occurrence of a noise impulse. The voltage sampled is stored in the capacitor of the sample-and-hold. A slope detector is responsive to the capacitor voltage for generating an output representative of the rate of variation of the capacitor voltage. A voltage-to-current converter is connected between the output of the slope detector and the capacitor for converting the voltage to a corresponding current and injecting the current to the capacitor when the rate of variation is positive and draining the current from the capacitor when the rate is negative.

REFERENCES:
patent: 4305042 (1981-12-01), Tanaka et al.
patent: 4311963 (1982-01-01), Watanabe et al.
patent: 4335322 (1982-06-01), Tanaka et al.
Patent Abstracts of Japan, vol. 6, No. 182, Sep. 18, 1982 & JP-A-57-095728 (Nippon Gakki Seizo K.K.) 14-06-1982.

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