Noise reducing output buffer circuit for an integrated circuit

Details Noise reducing output buffer circuit for an integrated circuit Noise reducing output buffer circuit for an integrated circuit

1990-05-30

1991-10-15

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307473, 307453, 307542, 36518905, H03K 19094

Patent

active

050577115

ABSTRACT:
An output buffer circuit for an integrated circuit for outputting an amplified signal from a sense amplifier which senses information stored in a memory cell of random access memory for improving operation of the integrated circuit is disclosed. The output buffer circuit comprises NAND gates ND1, ND2 operatively connected to the output of the sense amplifier to receive first and second output signals S1, S2, and operatively connected to receive a control signal .phi.1 from the integrated circuit which operates the memory cell to read. A MOSFET Q1 and a MOSFET Q2 are utilized with both MOSFETs turning on or off depending upon the signals applied to their gates. An output loading capacitor CL is operatively connected to the junction P4 and to the ground. A logic combination means 10 connected to junctions P1, P2 performs a logical combination of the signal applied through the junction P4 and the control signal .phi.1 applied to the input points of the logic combination means. An output means 20 is connected between the logic combination means 10 and the junction P4, thereby controlling the output level of the output buffer circuit to a middle level depending upon the signal from the logic combination means.

REFERENCES:
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patent: 4604731 (1986-08-01), Konishi
patent: 4724340 (1988-02-01), Sood
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patent: 4918339 (1990-04-01), Shigeo et al.
patent: 4950925 (1990-08-01), Doi et al.
patent: 4954729 (1990-09-01), Urai
patent: 5001369 (1991-03-01), Lee

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