Noise reducing circuit for CTD delay line

Details Noise reducing circuit for CTD delay line Noise reducing circuit for CTD delay line

1980-01-03

1982-03-02

Olms, Douglas W.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307607, 307221D, 333165, H04S 100

Patent

active

043179584

ABSTRACT:
In a delay circuit for delaying an input signal having a range extending over a higher- and a lower-frequency region, and in which a charge transfer device, such a bucket-brigade device, transfers a signal from an input to an output thereof in response to a clocking signal applied to the charge transfer device; a pre-emphasis circuit in advance of the charge transfer device emphasizes the input signal in its higher-frequency region, and a de-emphasis circuit after the charge transfer device emphasizes the signal at the output of the device in the lower-frequency region of the signal to compensate for the emphasis provided by the pre-emphasis circuit so that the delay circuit has a total response that is substantially flat. Such a delay circuit can be included in a stereophonic sound extending circuit to delay, by several milliseconds, one of left- and right-channel signals applied to a matrix circuit which provides extended signal components formed by combining each one of the left- and right-channel signals with a phase-inverted version of the other signal.

REFERENCES:
patent: 3236949 (1966-02-01), Atal et al.
patent: 4218585 (1980-08-01), Carver

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