Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2003-10-27
2004-12-14
Tra, Quan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06831500
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor circuit devices and, more particularly, to a voltage boosting circuit incorporated in a semiconductor circuit device.
2. Description of the Related Art
In recent years, there have been provided dynamic random access memories (DRAMs) which have a voltage boosting circuit in a chip and In which memory cells are driven through word lines or other wiring by using a voltage boosted by the voltage boosting circuit. There has been a challenge to reduce current noise in this kind of voltage boosting circuit. Conventional voltage boosting circuits designed to reduce current noise and to obtain a sufficiently high boosted voltage include an oscillator circuit which generates a plurality of oscillating signals having different timing from each other and a plurality of pumping circuits each having a capacitor of a small capacitance and transistors of a small size in corresponding to the respective oscillating signals.
FIG. 1
is a circuit diagram showing a conventional voltage boosting circuit. Referring to
FIG. 1
, boosting circuit
100
has oscillator circuit
120
, oscillator output signal latch circuit
130
, pumping circuit
140
, and boosted voltage level determination circuit
150
. Each of these circuits has the ground level as a reference potential and operates by an external power supply voltage VCC.
Oscillator output signal latch circuit
130
includes &phgr;
1
latch circuit
131
, &phgr;
2
latch circuit
132
, . . . , and &phgr;n latch circuit
13
n. Pumping circuit
140
includes &phgr;
1
pumping circuit
141
, &phgr;
2
pumping circuit
142
, . . . , and &phgr;n pumping circuit
14
n.
Signals &phgr;
1
-&phgr;n sent from oscillator circuit
120
are respectively given to &phgr;
1
-&phgr;n latch circuits
131
-
13
n. Signals &phgr;
1
A-&phgr;nA respectively sent from &phgr;
1
-&phgr;n latch circuits
131
-
13
n are respectively given to &phgr;
1
-&phgr;n pumping circuits
141
-
14
n. The outputs of &phgr;
1
-&phgr;n pumping circuits
141
-
14
n are connected to a common point, at which a boosted voltage VPP is generated. A signal VPUP sent from boosted level determination circuit
150
is given to oscillator circuit
120
and to the &phgr;
1
-&phgr;n latch circuits
131
-
13
n.
A desired voltage to be obtained by boosting is set in boosting circuit
100
. Boosted level determination circuit
150
compares the boosted voltage VPP provided from the boosting circuit
100
with a set voltage sets the signal VPUP to “H” when the boosted voltage VPP is lower than the set voltage, and sets the signal VPUP to “L” when the boosted voltage VPP is higher than the set voltage.
Oscillator circuit
120
sends a plurality of oscillating signals one after another at equally shifted times when the signal VPUP Is at “H”. For example, oscillator circuit
120
has inverters forming n stages (n: an odd number) connected in a chain configuration. Oscillator circuit
120
sends no oscillating signal when the signal VPUP is at “L”.
FIG. 2
is a circuit diagram showing an example of a basic configuration of the oscillator circuit. Referring to
FIG. 2
, Oscillator circuit
120
has a basic configuration in which odd number of inverters being connected in a ring-like chain. The inverters send signals &phgr;
1
-&phgr;n. In
FIG. 2
, a circuit portion relating to signal VPUP is not shown.
FIG. 3
is a timing chart showing the waveforms of signals &phgr;
1
-&phgr;n. Referring to
FIG. 3
, signals &phgr;
1
-&phgr;n are oscillating signals which have transition timings successively shifted and phases alternately reversed. The cycle of each of signals &phgr;
1
-&phgr;n is T. The time between edges of the adjacent signals, e.g., between the rising edge of the signal &phgr;
1
and the falling edge of signal &phgr;
2
is dT=T/(2×n), which is the waveform transmission time by the inverters.
Each of &phgr;
1
-&phgr;n latch circuits
131
-
13
constituting oscillator output signal latch circuit
130
uses signal VPUP as an enable signal. &phgr;
1
-&phgr;n latch circuits
131
-
13
n send signals &phgr;
1
-&phgr;n respectively as signals &phgr;
1
A-&phgr;nA when signal VPUP is at “H”. At this time, signals &phgr;
1
A-&phgr;nA are respectively in phase with signals &phgr;
1
-&phgr;n. &phgr;
1
-&phgr;n latch circuits
131
-
13
n hold the states of signals &phgr;
1
A-&phgr;nA when signal VPUP is at “L”.
&phgr;
1
-&phgr;n pumping circuits
141
-
14
n constituting the pumping circuit
140
are respectively supplied with signals &phgr;
1
-&phgr;nA and perform boosting operations in synchronization with signals &phgr;A-&phgr;nA. The output terminals of the &phgr;
1
-&phgr;n pumping circuits
141
-
14
n are connected to the common point, i.e., the output terminal of pumping circuit
140
, through which boosted voltage VPP is output.
FIG. 4
is a circuit diagram showing an example of the configuration of &phgr;
1
-&phgr;n pumping circuits. All of &phgr;
1
-&phgr;n pumping circuits are identical in configuration. In
FIG. 4
, &phgr;
1
pumping circuit is shown as a representative. Referring to
FIG. 4
, &phgr;
1
pumping circuit is constituted by inverters INV
0
and INV
1
, capacitor C
0
, and diodes DI
0
and DI
1
.
Signal &phgr;
1
A is given to inverter INV
0
. Inverters INV
0
and INV
1
are connected in series. The output terminal of inverter INV
1
and one terminal of capacitor C
0
are connected to each other at a connection point A. The other terminal of the capacitor C
0
, the cathode of diode DI
0
and the anode of diode DI
1
are connected to each other at a connection point B. External power supply voltage VCC is supplied to the anode of diode DI
0
. The cathodes of diodes DI
1
of &phgr;
1
-&phgr;n pumping circuits
141
-
14
n are connected to the common point through which boosted voltage VPP is output.
FIG. 5
is a timing chart showing the boosting operation of &phgr;
1
pumping circuit shown in FIG.
4
. Referring to
FIG. 5
, signal &phgr;
1
A is an oscillating signal having external power supply voltage VCC and reference voltage GND alternately sent. The signal waveform at the connection point A is slightly delayed from signal &phgr;
1
A.
When the potential at the connection point A is reference voltage GND level, the connection point B is precharged to external power supply voltage VCC through diode DI
0
. When a transition from reference voltage GND to external power supply voltage VCC is effected at the connection point A, the potential at the connection point B is increased by an amount corresponding to external power supply voltage VCC due to the coupling through capacitor C
0
. Accordingly, a transition of the potential at the connection point B is made from external power supply voltage VCC to a voltage (2×VCC) twice external power supply voltage VCC. Thus, &phgr;
1
pumping circuit
141
can generate boosted voltage VPP higher than external power supply voltage VCC. The circuit for control of diodes DI
0
and DI
1
shown in
FIG. 4
is not illustrated.
In general, the inverter is made by combining a Pch transistor (not shown) and an Nch transistor (not shown). Capacitor C
0
is charged by supply of a current caused by external power supply voltage VCC to flow through the Pch transistor of inverter INV
1
. Capacitor C
0
is discharged by the flow of a current from the connection point A to reference voltage GND through the Nch transistor of inverter INV
1
.
Similarly, the connection point B is precharged to external power supply voltage VCC by supply of a current caused by external power supply voltage VCC to flow to the connection point B through diode DI
0
.
The gate capacity of inverter INV
1
is charged and discharged by a charge current caused by external power supply voltage VCC to flow from inverter INV
0
to inverter INV
1
and a discharge current caused to flow from inverter INV
1
to reference voltage GND.
In the voltage boosting circuit, noise is caused due to the charge current from external power supply voltage VCC and the discharge current to reference vol
Miyano Kazutaka
Sato Tomohiko
Elpida Memory Inc.
Katten Muchin Zavis & Rosenman
Tra Quan
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