Noise pulse suppressing circuit in digital system

Details Noise pulse suppressing circuit in digital system Noise pulse suppressing circuit in digital system

1987-04-17

1988-11-22

Laroche, Eugene R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307520, 328111, H03K 522

Patent

active

047868236

ABSTRACT:
Noise pulses having both polarities which are superposed on an input signal having a binary state of H/L levels forming a rectangular waveform, are suppressed or eliminated before transferring the input signal to an output stage. A noise pulse suppressing circuit is provided which comprises a latch circuit, a counter circuit, and a logic circuit including NAND gates and INVERTERs. For the latch circuit and the counter circuit, D-type flip-flops are also utilized. The input signal is inputted to a data input terminal of a flip-flop of the latch circuit and outputted from the data output terminal thereof. The latch circuits are triggered by a pulse signal applied to a clock terminal thereof. The above triggering pulse signal is generated by the counter circuit and the logic circuit, and it has a short pulse waveform responding to the input signal but delayed. No pulse in the output is produced which corresponds to the noise pulses in the input signal.

REFERENCES:
patent: 3753135 (1973-08-01), Kastner et al.

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