Noise immunity circuitry for phase locked loops and delay...

Details Noise immunity circuitry for phase locked loops and delay... Noise immunity circuitry for phase locked loops and delay...

2008-05-13

2008-05-13

Kinkead, Arnold (Department: 2817)

Oscillators

Combined with particular output coupling network

C331S175000, C331S185000, C331S016000, C327S156000, C327S158000, C327S159000

Reexamination Certificate

active

11411186

ABSTRACT:
A clock circuit. The clock circuit includes a phase detector and an output unit. The phase detector is coupled to receive a reference clock signal and an output clock signal, and is configured to provide a phase signal indicative of a phase difference between the reference and output clock signals. The output unit is configured to provide the output clock signal, and is coupled to a first supply voltage node and a second supply voltage node. The output unit includes a biasing circuit and a voltage-controlled element. The biasing circuit is coupled to receive a control voltage based on the phase signal and is configured to generate a bias voltage based on the received control voltage. The voltage-controlled element is configured to adjust a parameter of the output clock signal based on the bias voltage. A supply-independent output clock is attained using this configuration.

REFERENCES:
patent: 6489822 (2002-12-01), Han
patent: 6873214 (2005-03-01), Harwood
patent: 6894546 (2005-05-01), Mika
patent: 6952125 (2005-10-01), Ahn
patent: 6998923 (2006-02-01), Melanson
patent: 7034590 (2006-04-01), Shin
patent: 7256657 (2007-08-01), Sanchez et al.

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