Noise elimination circuit

Details Noise elimination circuit Noise elimination circuit

2001-12-27

2003-09-16

Mis, David C. (Department: 2817)

Oscillators

Ring oscillators

C331S173000, C327S551000

Reexamination Certificate

active

06621359

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a noise elimination circuit, and in particular, to an improved noise elimination circuit which can eliminate all noise of a reset signal of a microprocessor or an input signal effective in a specific logic level.
2. Description of the Background Art
FIG. 1
is a circuit diagram illustrating a conventional noise elimination circuit.
Referring to
FIG. 1
, the conventional noise elimination circuit includes: an inverter INV
1
receiving a reset bar signal /RESET, and outputting an inverted signal to a node Nd
1
; a noise elimination unit
10
receiving the signal transmitted to the node Nd
1
, for eliminating noise of the signal, and outputting the resultant signal to a node Nd
2
; a NOR gate NOR
1
NORing the signals of the nodes Nd
1
, Nd
2
; an AND gate AND
1
ANDing the signals of the nodes Nd
1
, Nd
2
; and an RS latch circuit unit
12
receiving the output signal from the NOR gate NOR
1
as a set signal and the output signal from the AND gate AND
1
as a reset signal, and generating a chip reset signal to an output terminal Q.
In the conventional noise elimination circuit, when the reset bar signal /RESET is enabled in a low level, the signal of the node Nd
1
is transited to a high level by the inverter INV
1
. The signal of the node Nd
1
(high) outputs a high level signal to the node Nd
2
through the noise elimination unit
10
after a delay time t
1
. Accordingly, the reset input of the RS latch circuit unit
12
is enabled in a high level, thus clearing the RS latch circuit unit
12
.
Here, the noise elimination unit
10
eliminates noise of the reset bar signal /RESET, so that an unwanted chip reset signal cannot be generated due to noise in the signal.
FIG. 2A
is a circuit diagram illustrating a noise elimination unit using the R-C delay shown in
FIG. 1
, and
FIG. 2B
is a circuit diagram illustrating a noise elimination unit using an inverter and capacitor delay shown in FIG.
1
.
As illustrated in
FIG. 2A
, the conventional noise elimination unit
10
includes: an inverter INV
2
and a resistor R
1
connected in series between the nodes Nd
1
, Nd
3
; a capacitor C
1
connected between the node Nd
3
and the ground voltage Vss; a resistor R
2
connected between the nodes Nd
3
, Nd
4
; a capacitor C
2
connected between the node Nd
4
and the ground voltage Vss; a resistor R
3
connected between the nodes Nd
4
, Nd
5
; a capacitor C
3
connected between the node Nd
5
and the ground voltage Vss; and an inverter INV
3
connected between the nodes Nd
5
, Nd
2
.
As depicted in
FIG. 2B
, the conventional noise elimination unit
10
using the inverter and capacitor delay includes: an inverter INV
4
connected between the nodes Nd
1
, Nd
6
; a capacitor C
4
connected between the node Nd
6
and the ground voltage Vss; an inverter INV
5
connected between the nodes Nd
6
, Nd
7
; a capacitor C
5
connected between the node Nd
7
and the ground voltage Vss; an inverter INV
6
connected between the nodes Nd
7
, Nd
8
; a capacitor C
6
connected between the node Nd
8
and the ground voltage Vss; and an inverter INV
7
connected between the nodes Nd
8
, Nd
2
.
The operation of the conventional noise elimination unit
10
will now be explained.
When the signal of the node Nd
1
is inputted to the noise elimination unit
10
, the signal is outputted to the node Nd
2
without noise after a predetermined delay time t
1
in the noise elimination unit
10
. That is, when the signal of the node Nd
1
has a smaller noise period than the delay time t
1
, the noise elimination unit
10
filters the signal to prevent influence of the noise on the signal of the node Nd
2
.
Accordingly, the reset input signal of the RS latch circuit unit
12
(
FIG. 1
) has a low level, and thus the output signal Q is maintained as it is.
However, the conventional noise elimination circuit has a disadvantage in that when noise is consecutively generated before the delay time, the noise elimination unit does not successfully eliminate noise.
The problem of the conventional noise elimination circuit will now be explained with reference to
FIGS. 3A and 3B
.
Referring to
FIG. 3A
, when noise t
2
-t
4
is consecutively inputted to the reset bar signal /RESET after the delay time t
1
, the signals of the nodes Nd
3
, Nd
4
, Nd
5
of the noise elimination unit
10
gradually reduce the corresponding potential levels. As shown in FIG.
3
A(f), the signal outputted to the node Nd
2
through the inverter INV
3
has an undesirable high level, as shown by the spike.
The high level signal of the node Nd
2
converts the reset input signal of the RS latch circuit unit
12
into a high level signal, and thus converts the output signal Q into a high level signal. That is, the chip reset signal is generated due to unwanted noise, which causes a mis-operation of the circuit.
As illustrated in
FIG. 3B
, when noise t
5
-t
6
is consecutively inputted to the reset bar signal /RESET after the delay time t
1
, the signals of the nodes Nd
6
, Nd
7
, Nd
8
of the noise elimination unit
10
gradually reduce the corresponding potential levels. As shown in FIG.
3
B(f), the signal outputted to the node Nd
2
through the inverter INV
7
has an undesirable high level.
The high level signal of the node Nd
2
converts the reset input signal of the RS latch circuit unit
12
into a high level signal. Therefore, the chip reset signal is generated due to unwanted noise, thereby causing a mis-operation of the circuit.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a noise elimination circuit that can eliminate all noise of a reset signal of a microprocessor or an input signal effective in a specific logic level, by varying a filtering time through a ring oscillator and a frequency division circuit.
In order to achieve the above-described object of the present invention, there is provided a noise elimination circuit including: a ring oscillator unit for receiving first and second signals and generating a pulse signal according to the first signal, and stopping generation of the pulse signal when the first and the second signals have a first potential level; and a frequency division unit for receiving an output signal of the ring oscillator unit and then, N times frequency-dividing to generate the signal to the second signal, and being reset by the first signal. When the first potential is at a logic high level, and the second potential is at a logic low level. Conversely, when the first potential is at a logic low level, and the second potential is at a logic high level.
Preferably, the ring oscillator unit includes: a third inverter for inverting a signal of the first node, and outputting the inverted signal to a third node; an OR gate for ORing the signals of the third node and the second node, and outputting the resultant signal to a fourth node; a fourth inverter for inverting a signal of a fifth node according to the signal of the fourth node; a resistor connected between the output terminal of the fourth inverter and a sixth node; fifth and sixth inverters connected in series between the sixth node and the fifth node; a capacitor connected between the fifth node and the sixth node; an NMOS transistor for discharging a signal of the sixth node into the ground voltage according to the signal of the fourth node; and seventh and eight inverters connected in series between the fifth node and the seventh node.
In addition, the frequency division of the frequency division circuit unit is dependent upon the structure and design of the ring oscillator unit.
According to another aspect of the present invention, a noise elimination circuit includes: a first inverter receiving a reset bar signal, and outputting an inverted signal to a first node; a noise elimination unit receiving the signal of the first node, eliminating all noise of the signal, and outputting the resultant signal to a second node; a second inverter inverting the signal of the first node; an AND gate ANDing the signal of the first nod

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