Noise controlled output buffer

Details Noise controlled output buffer Noise controlled output buffer

1987-06-25

1989-04-18

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307473, 307270, 3072961, 307542, H03K 1716, H03K 17284, H03K 17687, H03K 19003

Patent

active

048230294

ABSTRACT:
An integrated circuit has output buffers whose switching rise and/or fall times are controlled to compensate for process speed and other variations. Therefore, an integrated circuit fabricated by a "fast" process does not generate excessive noise, while integrated circuits fabricated by a "slow" process still obtain adequate speed. A control voltage generated by an on-chip voltage divider network is applied to the gate of a control transistor to provide the compensation.

REFERENCES:
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patent: 4425517 (1984-01-01), Smith
patent: 4567378 (1986-01-01), Raver
patent: 4585958 (1986-04-01), Chung et al.
patent: 4593206 (1986-06-01), Neidorff et al.
patent: 4620310 (1986-10-01), Lvovsky et al.
patent: 4621208 (1986-11-01), Van Tran
patent: 4721866 (1988-01-01), Chi et al.
patent: 4723108 (1988-02-01), Murphy et al.
IBM J. Res. Develop, vol. 25, No. 3, May 1981, "Delay Regulation-A Circuit Solution to the Power/Performance Tradeoff", E. Berndlmaier, J. A. Dorler, J. M. Mosley, S. D. Weitzel, pp. 135 through 141.

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