Noise checking method and apparatus and computer-readable...

Data processing: measuring – calibrating – or testing – Measurement system – Measured signal processing

Reexamination Certificate

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Details

C702S069000, C702S074000, C702S075000, C702S076000, C702S079000, C702S182000

Reexamination Certificate

active

10979117

ABSTRACT:
The apparatus reduces the amount of correction for noise value error, so as to reduce work needed for correction to ensure error avoidance, and to improve the freedom of layout design, and to reduce load on DA. Based on a timing chart of signal transfer on each wire, the last edge appearance timing in the signal waveform of a victim whose noise value exceeds a limit value is compared with the last edge appearance timing in the signal waveform of an aggressor, to evaluate the noise value error in the victim. The apparatus is used in static noise checking of cell arrangement and inter-cell wiring after such cell arrangement and inter-cell wiring are performed at design of integrated circuits such as LSIs.

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patent: 7031889 (2006-04-01), McBride
patent: 2002/0147553 (2002-10-01), Shimazaki et al.
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patent: 2004/0041281 (2004-03-01), Sakai et al.
patent: 2005/0283668 (2005-12-01), Ishikawa
patent: 8-278992 (1996-10-01), None
patent: 10-96762 (1998-04-01), None
patent: 2001-217315 (2001-08-01), None
patent: 2002-358341 (2002-12-01), None

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