Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2005-07-05
2005-07-05
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S013000, C716S030000, C716S030000, C716S030000, C379S022000, C455S501000, C370S201000
Reexamination Certificate
active
06915249
ABSTRACT:
In order to achieve augmentation of the accuracy in calculation of noise and augmentation of the accuracy in a noise check which is performed, for example, when an electronic circuit is designed and further realize significant reduction of the time required for a noise check and augmentation of the operation efficiency by reduction of the man-hours of a designer in a noise analysis, a noise checking apparatus includes a model production section (3) for producing a simulation model of a circuit portion relating to a noticed wiring line, a simulation section (4) for performing a simulation using the simulation model to calculate a signal waveform which propagates in the noticed wiring line and calculate a noise waveform superposed on the signal waveform for each kind of noise, a noise waveform synthesis section (5) for synthesizing the signal waveform and the noise waveforms with generation timings of the noise waveforms taken into consideration to obtain a noise composite waveform, and a noise checking section (6) for performing noise checking based on the noise composite waveform.
REFERENCES:
patent: 5243547 (1993-09-01), Tsai et al.
patent: 5481695 (1996-01-01), Purks
patent: 5502644 (1996-03-01), Hamilton et al.
patent: 5568395 (1996-10-01), Huang
patent: 5706477 (1998-01-01), Goto
patent: 5751163 (1998-05-01), Tang et al.
patent: 5751597 (1998-05-01), Okano et al.
patent: 5867810 (1999-02-01), Miura et al.
patent: 5983006 (1999-11-01), Carlson et al.
patent: 5999714 (1999-12-01), Conn et al.
patent: 6028989 (2000-02-01), Dansky et al.
patent: 6106567 (2000-08-01), Grobman et al.
patent: 6128769 (2000-10-01), Carlson et al.
patent: 6212490 (2001-04-01), Li et al.
patent: 6278951 (2001-08-01), Sato
patent: 62-53372 (1987-04-01), None
patent: 4-256072 (1992-09-01), None
patent: 6-243193 (1994-09-01), None
patent: 7-152824 (1995-06-01), None
patent: 8-297689 (1996-11-01), None
patent: 10-74216 (1998-03-01), None
patent: 10-97511 (1998-04-01), None
patent: 11-45294 (1999-02-01), None
“Dictionary.com: 11 entries found for filter” http://www.dictionary.com/search?q=filter. Download from web Sep. 23, 2003.
“Dictionary.com: 6 entries found for synthesis” http://www.dictionary.com/search?q=synthesis. Download from web Sep. 23, 2003.
“Dictionary.com: 4 entries found for synthesize” http://www.dictionary.com/search?q=synthesize. Download from web Sep. 23, 2003.
“Dictionary.com: 3 entries found for crosstalk” http://www.dictionary.com/search?q=crosstalk. Download from web Sep. 23, 2003.
Rhodes, D.L. “Parallel Computation for Microwave Circuit Simulation”. IEEE Transactions on Microwave Theory and Techniques. vol. 45, Issue 5. May '97. pp. 587-592.
Lipman, Jim. “Board-Level Signal-Integrity Analysis: Sooner is Better” EDN Access. Jul. 16, 1998. http://www.e-insite.net/ednmag/archives/1998/071698/15df2.htm.
Steinberg, C. and Wilson, I. “Simulation Programs Iron Out Transmission-Line Effects”. EDN Access. Mar. 3, 1994. http://www.e-insite.net/ednmag/archives/1994/030394/05df2.htm.
Matsui et al. “Electrical Design Techniques for High-Speed Circuit Boards”. 8th IEEE/CHMT Int'l Electronic Manufacturing Technology Symposium, 1990. May 9, 1990. pp. 234-243.
Becker et al. “FDTD Modeling of Noise in Computer Packages”. Proceedings, 1993 IEEE Multi-Chip Module Conference. Mar. 18, 1993. pp. 123-127.
Gao, et al. “Minimum Crosstalk Channel Routing”. 1993 IEEE/ACM Int'l Conf. On CAD. Nov. 11, 1993. pp. 692-696.
John, et al. “Methods for Simulation of Reflection and Crosstalk Effects on Printed Circuit Boards”. 9th Int'l Conference on Electromagnetic Compatibility, 1994. Sep. 7, 1994. pp. 217-224.
Kyoung-Son, et al. “A Segment Rearrangement Approach to Channel Routing Under the Crosstalk Constraints”. 1994 IEEE Asia-Pacific Conference on Circuits and Systems. Dec. 8, 1994. pp. 536-541.
Huq, Syad. “Understanding and Using IBIS models for Signal Integrity Analysis”. Presented at High-Level Electronic System Design Conference (HESDC '97). Oct. 7-9, 1997. http://www.eigroup.org/ibis/hesdccvr.htm.
“IBIS”, Printed Circuit Design Magazine, Apr. 1997. http://signalintegrity.com/Pubs/straight/ibis.htm.
I/O Buffer Information Specification (IBIS) Version 3.0, (Jun. 12, 1997), http://www.eigroup.org/ibis/specs.htm.
ACCEL Technologies, Inc. “ACCEL Signal Integrity™ User Guide”. 1998.
IEE, Conference Publication No. 396; pp. 217-224, 1994. Cited in the Search Rpt.
Electronic Parts and Materials, Industry Information Center, Oct. 1, 1998, vol. 37, No. 19, pp. 72-76. Cited in the Search Report.
Gotou Kazunari
Iwakura Yoshiyuki
Kanei Kazuyoshi
Sato Toshiaki
Sato Toshiro
Sharon Ayal
Teska Kevin J.
LandOfFree
Noise checking method and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Noise checking method and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Noise checking method and apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3423219