No-reset option in a batch billing system

Electrical computers and digital processing systems: interprogra – Event handling or event notification

Reexamination Certificate

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Details

C718S101000, C718S102000, C714S010000, C705S034000

Reexamination Certificate

active

07412707

ABSTRACT:
A system for processing a batch which is distributed into a plurality of independent segments. A preferred embodiment of this invention calls for implementation on a symmetrical multiprocessing platform, however, the invention is also applicable to massively parallel architectures as well as uniprocessor environments. Each segment comprises a plurality of discrete events, each discrete event comprising a plurality of sub-events to be processed. The system operates to process each discrete event within each segment sequentially and each sub-event within each discrete event sequentially. The plurality of segments may be processed on an uniprocessor, an SMP system or an MPP system. By balancing the number of discrete events in each segment using a “coarse grain” approach, a flexible but efficient use of processor availability is obtained.

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