No-chip debug peripheral which uses externally provided instruct

Details No-chip debug peripheral which uses externally provided instruct No-chip debug peripheral which uses externally provided instruct

1989-04-03

1991-10-01

Lee, Thomas C.

Boots, shoes, and leggings

3642392, 3642548, 364967, G06F 1100, G06F 1130

Patent

active

050539493

ABSTRACT:
A data processing system having a debug peripheral is provided. The debug peripheral is coupled to a central processing unit and memory via an internal communications bus. The debug peripheral is a single-word dual port memory with parallel read-write write access on one side, and synchronous, full-duplex serial read-write access on the other side. The serial side of the debug peripheral is connected to external emulation hardware by means of a three-pin synchronous serial interface. The parallel access is via a connection to a core central processing unit (CPU) internal communications bus. The debug peripheral is addressed at sixteen adjacent locations in the CPU memory space. During a debug interlude, the debug peripheral assumes control of the CPU by providing an interrup signal to the CPU, and thereby causing the CPU to fetch instructions directly from the debug peripheral. The debug peripheral receives instructions from the external emulation hardware, and provides the debug instructions to the CPU, in response to an instruction address provided by the CPU.

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Embedded Bliss for Emulation, Huffman et al., 02-01-87, Electronic Products pp. 20-21.

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