NMOS transistor having inversion layer source/drain contacts

Details NMOS transistor having inversion layer source/drain contacts NMOS transistor having inversion layer source/drain contacts

1989-06-30

1991-02-19

James, Andrew J.

357 234, 357 2312, H01L 2910

Patent

active

049948695

ABSTRACT:
A transistor (42) is provided having a gate conductor (44) formed adjacent a semiconductor substrate (46) and separated therefrom by a gate insulator (48). Sidewall spacers (52, 54) are formed at the sides of gate conductor (44) and adjacent semiconductor substrate (46). Diffused regions (56, 58) are formed within semiconductor substrate (46) in order to provide source/drain regions for transistor (42). Positive charges from radiation are trapped within sidewall spacers (52, 54) thereby attracting negative charges from semiconductor substrate (46) such that a negative charge layer is created between diffused region (56) and gate edge (50a) and also between diffused region (58) and gate edge (50b).

REFERENCES:
Sze, Semiconductor Devices: Physics and Technology, 1985, pp. 197-200.

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