NMOS driver circuit for CMOS circuitry

Details NMOS driver circuit for CMOS circuitry NMOS driver circuit for CMOS circuitry

1989-03-24

1990-09-11

Hille, Rolf

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 40, 307448, 307475, 307279, 307270, 307446, H01L 2702

Patent

active

049566911

ABSTRACT:
A driver circuit, which uses two serially connected enhancement mode n-channel MOS transistors in which the pullup transistor of the two transistors has no p-type implant in the channel region thereof and the pulldown transistor of the pair is a normlal enhancement mode transistor having a p-type threshold control implant in the channel thereof, is useful as a driver circuit for CMOS circiuts. The pullup transistor is designed to have a threshold of about 0 volts at zero back gate bias and the pulldown transistor is designed to have a threshold voltage of about 0.7 volts at zero back gate bias.

REFERENCES:
patent: 4553051 (1985-11-01), Prater

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