Nitridization of STI sidewalls

Details Nitridization of STI sidewalls Nitridization of STI sidewalls

2000-07-28

2002-03-05

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S400000, C438S424000, C438S437000, C438S149000

Reexamination Certificate

active

06352906

ABSTRACT:

FIELD OF THE INVENTION
The field of the invention is integrated circuit fabrication, in particular fabrication on SOI wafers.
BACKGROUND OF THE INVENTION
Shallow trench isolation (STI) has become standard in submicron integrated circuit processing, including silicon on insulator (SOI) processing, because of its size benefits.
A problem in small size devices, especially narrow devices (less than about 500 nm) is that of maintaining a stable threshold voltage.
SUMMARY OF THE INVENTION
The invention relates to an SOI integrated circuit employing shallow trench isolation, in which the walls of the transistor active area have a nitridized oxide layer grown on them, thereby preventing the diffusion of dopants out of the transistor body.


REFERENCES:
patent: 5447488 (1995-09-01), Fahey et al.
patent: 5811347 (1998-09-01), Gardner et al.
patent: 5985735 (1999-11-01), Moon et al.
patent: 6225659 (2001-05-01), Liu

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