Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Patent
1996-10-28
1998-07-07
Dang, Trung
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
438225, 438227, 438228, 438229, 438975, H01L 2176
Patent
active
057768161
ABSTRACT:
A method of fabricating alignment marks on an integrated circuit device including steps of: forming first pad oxide layer and first nitride layer on a P-type semiconductor substrate; coating and patterning first photoresist layer by lithography; partially etching first nitride layer to form first nitride pattern by first photoresist etching mask; and ion implanting N-type ions to form an N-doped region; coating and patterning second photoresist layer by lithography; partially etching first nitride pattern to form second nitride pattern; and ion implanting P-type ions to formed a P-doped region. Next, performing thermally drive in N-type and P-type impurities to form N-well and P-well regions, and growing an oxide layer simultaneously. Finally, the height difference between the oxide layer and the second nitride pattern producing a ladder topography can be used as an alignment mark for the succeeding lithographic processes.
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patent: 5441902 (1995-08-01), Hsieh et al.
patent: 5460984 (1995-10-01), Yoshida
patent: 5478762 (1995-12-01), Chao
Chen Chwan Chao
Liu Chia Chen
Dang Trung
Holtek Microelectronics Inc.
Liauh W. Wayne
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