Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Reexamination Certificate
1997-07-10
2002-06-18
Talbot, Brian K. (Department: 1762)
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
C427S305000, C427S383100, C427S438000, C438S592000, C438S630000, C438S649000, C438S655000, C438S663000, C438S664000, C438S678000, C438S682000
Reexamination Certificate
active
06406743
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to the fabrication of interconnect structures for VLSI semiconductor devices and particularly to the fabrication of Ni silicide interconnects and more particularly to the formation of Nickel Silicide interconnects by electroless Ni deposition on polysilicon.
2) Description of the Prior Art
Individual semiconductor devices in VLSI integrated circuits are interconnected by means of one or more patterned conductive layers overlying the semiconductor devices. It is particularly advantageous to provide a plurality of patterned conductive layers separated from one another and from the underlying semiconductor devices by layers of insulating material. This practice permits a higher density of interconnections per unit area than can be provided by a single patterned conductive layer, and simplifies design by permitting interconnection paths implemented in one conductive layer to cross over interconnection paths implemented in other conductive layers.
Multilevel interconnection structures are conventionally made by alternately depositing and patterning layers of conductive material, typically aluminum alloys such as Al—Si, and layers of insulating material, typically SiO2. The patterning of underlying layers defines a nonplanar topography which complicates reliable formation of overlying layers. In particular, the non-planar topography of underlying conductive layers is replicated in overlying insulating layers to provide vertical steps in the insulating layers. Moreover, small holes are formed in the insulating layers to permit interconnection to underlying conductive layers or device contacts. The subsequent formation of conductive layers overlying the nonplanar topography of the insulating layers is complicated by thinning of the conductive layers at the tops of the steps, cusping or microcracking of the conductive layers at the bottoms of the steps, and formation of voids in the conductive layers in small via and contact holes, all of which can lead to high resistance interconnections or undesired open circuits. Moreover, uneven formation of the conductive layers reduces the resistance of the patterned conductive material to electromigration, reducing the reliability of the completed integrated circuit.
In addition to the insulating/topology issues discuss above, there is a need to improve the metal silicide contacts. In particular, the resistivity of the contacts must be reduced to improve circuit performance. Presently, TiSi
2
is a common contact metal. The resistance of TiSi
2
should be reduced. Nickel silicide is one of the potential alternatives for replacing TiSi
2
because the sheet resistance increases significantly as the line width reduces to the deep submicron range. It has been found that TiSi
2
-polycide has an abrupt increase in sheet resistance caused by large inter grain layer which increases the sheet resistance in narrow lines. See “Analysis of Resistance Behavior in Ti- and Ni-Salicided Polysilicon Films”, IEEE Transactions on Electron Devices, vol., 41, No. 12, December 1994 p. 2305-2316. However, the nickel silicide does not have such significant resistance degradation effect. Conventionally, the nickel silicide was formed by depositing Ni film on the Si substrate by evaporation, followed by annealing in a controlled environment or with rapid thermal processing (RTP). A short coming with this method of Ni Six formation is that NiSix needs to be wet etched to remove unreacted Ni layer. This adds cost to the product costs.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 4,425,378 (Maher) shows a method of electroless Ni plating. U.S. Pat. No. 4,954,214(Ho) shows a method of forming interconnect structures using a nickel deposited by selective electroless Ni plating. See Col. 7, lines 64 to Col. 8, lines 16. Also, Kikkawa and Sakai “0.35 &mgr;m Technologies in Japan” Mat. Res. Soc. Sump Process Vol. 404 1996 Materials Research Society p. 199-298, and Ohguro, et al., “Analysis of Resistance Behavior in Ti- and Ni-Salicided Polysilicon Films”, IEEE Transactions on Electron Devices, Vol., 41, No. 12, December 1994 p. 2305-2316, discuss relevant prior art.
There is a need for an alternative method by which the nickel can be deposited by electroless plating, and subsequently annealing to form a low resistivity nickel silicide.
There is a need to develop an improved electroless deposition that can selectively deposit on a catalysis surface and not affect the underlying isolation layer (SiO
2
)
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a Ni-silicide Formation on Polysilicon using electroless Ni Deposition technique.
It is an object of the present invention to provide a method for fabricating a Ni-silicide interconnect on Polysilicon using electroless Ni Deposition technique.
It is an object of the present invention to form a Ni-salicided structure using electroless Ni deposition technique and rapid thermal anneal (RTA) technique.
To accomplish the above objectives, the present invention provides a method for Nickel silicide
36
formation by Electroless Ni deposition on Polysilicon
30
and rapid thermal annealing. The invention has four preferred electroless Ni plating electroless solutions. The invention also has a preferred RTA process performed at about 600° C. This anneal produces a low resistivity Ni silicide
36
A (NiSi—about 1:1 Ni to Si ratio) that has a low resistivity without any agglomeration. The Ni silicide interconnect of the invention is preferably used in a salicide process in a semiconductor device as shown in FIG.
10
.
The method of the invention preferably comprises the following steps:
a) See FIG.
1
—forming a first insulting layer over a substrate;
b) See FIG.
2
—forming a polysilicon layer
30
over the substrate
10
;
c) See FIG.
3
—patterning the polysilicon layer
30
to form interconnections;
d) See FIG.
4
—activating the surface of the polysilicon layer by bringing into contact a solution of PdCl
2
in HF and CH
3
COOH for between about 8 and 12 sec (tgt 10 seconds) at temperature between 60 and 70° F. (room temperature);
e) See FIG.
5
—selectively electroless depositing Ni onto the surface of the polysilicon layer forming a Ni layer over the polysilicon layer (using the Pd particles as a catalyst); the selectively electroless depositing Ni performed at the following conditions: (solution 1) a Nickel sulfate concentration between about 24 and 35 g/l) (tgt.=30 g/L), Sodium Hypophosphite at a concentration between about 7.5 and 10 g/l (tgt=7.5 g/l) ammonium chloride at a concentration between about 6 and 10 g/l (tgt=8); Ethylene diamine (complexing agent) at a concentration between about 50 and 70 (tgt=600 g/l) and at a temperature between about 70 and 72° C. (tgt=72° C.) and at a pH between about 9.8 and 10.2 (tgt=10);
f) See FIG.
6
—Rapidly thermally annealing the substrate forming a Nickel silicide layer
36
between the Ni Layer
40
and the polysilicon layer
30
; the rapid thermal anneal performed at a temperature in a range of between about 400 and 750° C. (tgt=600° C.) for a time in a range of between about 39 and 60 seconds (tgt=40 sec) and with a nitrogen flow in a range of between about 2 and 5 slm (tgt=5 slm); the Ni silicide layer
36
is preferably composed of NiSi
36
A; and
g) See FIG.
7
—removing by wet etching the Ni layer
40
thereby leaving the Ni silicide layer
36
the polysilicon layer
30
over the substrate.
The method of this invention has many advantages, such as excellent uniformity, fast deposition rate and superior selectivity. The RTA process of the invention produces low resistivity a NiSi layer
36
A without a
Huang Tzuen-Hsi
Lee Chwan-Ying
Ackerman Stephen B.
Industrial Technology Research Institute
Saile George O.
Stoffel William J.
Talbot Brian K.
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