Neutralization techniques for differential low noise amplifiers

Details Neutralization techniques for differential low noise amplifiers Neutralization techniques for differential low noise amplifiers

2007-08-14

2007-08-14

Nu Ton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Nonlinear amplifying circuit

C330S260000

Reexamination Certificate

active

11157246

ABSTRACT:
An differential LNA has first and second input MOS transistors, with differential inputs applied to their respective control gates and differential outputs taken at their respective drains. The gate-to-drain, Cgd, feedback capacitances of the first and second input MOS transistors are neutralized by respective gate-to-source, Cgs, capacitances in the two neutralizing MOS transistors. A first neutralizing MOS transistor has its control gate coupled to the control gate of the first input MOS transistor, its source node coupled to the drain node of the second input MOS transistor, and its drain node coupled to a fixed potential. A second neutralizing MOS transistor has its control gate coupled to the control gate of the second input MOS transistor, its source node coupled to the drain node of the first input MOS transistor, and its drain node coupled to the same fixed potential. In this manner, similar and opposite potential differences between the gate-and-drain and the drain-and-source regions of the first input MOS transistor are reproduced in gate-and-drain and drain-and-source regions of the first neutralizing MOS transistor. A similar affect is produced in the second input and second neutralizing MOS transistor.

REFERENCES:
patent: 6624699 (2003-09-01), Yin et al.
patent: 6819182 (2004-11-01), Sibrai
patent: 7082293 (2006-07-01), Rofougaran et al.
patent: 2004/0232982 (2004-11-01), Ichitsubo et al.
The Design of CMOS Radio-Frequency Integrated Circuits, Second Edition; Thomas H. Lee, Cambridge University Press 1998, pp. 294-297.

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