Neutral impurities to increase lifetime of operation of semicond

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

357 233, 357 238, 357 20, 357 63, H01L 2910

Patent

active

051344475

ABSTRACT:
In order to reduce the rate of (hot charge-carrier) degradation of semiconductor devices formed in a semiconductor body, a neutral impurity--such as germanium in silicon MOS transistors--is introduced into the body in a neighborhood of an intersection of a p-n junction with a surface of the body.

REFERENCES:
patent: 4613882 (1986-09-01), Pimbley et al.
patent: 4636822 (1987-01-01), Codella et al.
patent: 4680603 (1987-07-01), Wei et al.
patent: 4683645 (1987-08-01), Naguib et al.
patent: 4835112 (1989-05-01), Pfiester et al.
patent: 4837173 (1989-06-01), Alvis et al.
patent: 4843023 (1989-06-01), Chiu et al.
IEEE Transactions on Electron Devices, vol. 35, No. 5, May 1988, "Optimization of the Germanium Preamorphization Conditions for Shallow-Junction Formation", M. C. Ozturk et al, pp. 659-668.
Appl. Phys. Lett., vol. 52(12), Mar. 21, 1988, "Very Shallow p.sup.+ -n Junction Formation by low-energy BF.sub.2.sup.+ Ion Implantation Into Crystalline and Germanium Preamorphized Silicon", by M. C. Ozturk et al, pp. 963-965.
Appl. Phys. Lett, vol. 52(4), Jan. 25, 1988, "Electrical Properties of Shallow p.sup.+ -n Junctions Formed by BF.sub.2 Ion Implantation in Germanium Preamorphized Silicon", by M. C. Ozturk et al, pp. 281-283.
Appl. Phys. Lett, vol. 51(15), Oct. 12, 1987, "Defect Annihilation in Shallow p.sup.+ Junctions Using Titanium Silicide", D. S. Wen et al, pp. 1269-1271.
Appl. Phys. Lett., vol. 49(19), Nov. 10, 1986, "Elimination of End-of-range and Mask Edge Lateral Damage in Ge+ Preamorphized, B.sup.+ Implanted Si", A. C. Ajmera et al, pp. 1269-1271.
IEEE Electron Device Letters, vol. 9, No. 7, Jul. 1988, "Improved MOSFET Short-Channel Device Using Germanium Implantation", James R. Pfiester, et al, pp. 343-346.
IEEE CH2515-5/87/0000-0740, 1987, "Novel Germanium/Boron Channel-Stop Implantation for Submicron CMOS", J. R. Pfiester et al, pp. 740-743.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Neutral impurities to increase lifetime of operation of semicond does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Neutral impurities to increase lifetime of operation of semicond, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Neutral impurities to increase lifetime of operation of semicond will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1689772

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.