Patent
1993-10-27
1996-06-04
MacDonald, Allen R.
395 24, 395 27, G06F 1516, G06F 1518
Patent
active
055241751
ABSTRACT:
A general neuro-computer and system using it is capable of executing a plurality of learning algorithms, providing an instruction execution speed comparable with a hard wired system, and practically neglecting a time required for rewriting microprograms. The neuro-computer is constituted by a neuron array having a plurality of neurons, a control storage unit for storing microinstructions, a parameter register, a control logic, and a global memory. A host computer as a user interface inputs information necessary for the learning and execution of the neuro-computer to the system, the information including learning algorithms, neural network architecture, the number of learnings, the number of input patterns, input signals, and desired signals. The information inputted from the host computer is transferred via a SCSI to the neuro-computer to perform a desired neural network operation.
REFERENCES:
patent: 4796199 (1989-01-01), Hammerstrom et al.
patent: 4918617 (1990-04-01), Hammerstrom et al.
patent: 5109475 (1992-04-01), Kosaka et al.
patent: 5131072 (1992-07-01), Yoshizawa et al.
patent: 5165010 (1992-11-01), Masuda et al.
patent: 5170463 (1992-12-01), Fujimoto et al.
patent: 5204938 (1993-04-01), Skapura et al.
patent: 5212767 (1993-05-01), Higashino et al.
patent: 5214743 (1993-05-01), Asai et al.
Symople-x: A General-Purpose Neurocomputer Architecture Ramacher IEEE/18-21 Nov. 1991.
Neurocomputer Interfaces and Performance Measures Hecht-Nielsen, IEEE 8-11 May 1989.
Digital VLSI Multiprocessor Design for Neurocomputers Chang et al. IEEE/7-11 Jun. 1992.
An Integrated Neurocomputing System Nigri et al. IEEE, 8-14 Jul. 1991.
Design of Parallel Hardware Neural Network Systems from Custom Analog VLSI/Building Block Chips.
Eberhardt et al. IEEE 18-22 Jun. 1989.
"Learning Internal Representations by Error Propagation", Parallel Distributed Processing, D. Rumelhart, et al., vol. 1 Foundations, Chapter 8, pp. 318-362.
"A Wafer Scale Integration Neural Network Utilizing Completely Digital Circuits", M. Yamada, et al., Central Research Lab., Hitachi, Ltd., pp. 55-60.
"High-Speed Learning Neuro-WSI", N. Asai, et al., Central Research Lab., Hitachi, Ltd., pp. 87-92.
"CNAPS", Adaptive Solutions, VSLI, pp. 144-151.
"The self-Organizing Map", T. Kohonen, IEEE 1990, Invited Paper, pp. 419-435.
Asai Mitsuo
Hashimoto Masashi
Kuwabara Yoshihiro
Moki Keiji
Ochiai Tatsuo
Dorvil Richemond D.
Hitachi , Ltd.
Hitachi Micro Computer System, Ltd.
MacDonald Allen R.
LandOfFree
Neuro-computer system for executing a plurality of controlling a does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Neuro-computer system for executing a plurality of controlling a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Neuro-computer system for executing a plurality of controlling a will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-391407