Data processing: artificial intelligence – Neural network – Structure
Reexamination Certificate
2000-02-28
2003-03-25
Davis, George B. (Department: 2121)
Data processing: artificial intelligence
Neural network
Structure
C706S034000
Reexamination Certificate
active
06539368
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of computer science and can be used for neural network emulation and real-time digital signal processing.
BACKGROUND INFORMATION
Network Algorithms Implementation/Y. P. Ivanov and others (Theses of reports of the Second Russian Conference <<Neural Computers And Their Application)>>, Moscow, Feb. 14, 1996) //Neurocomputer.—1996.—No.1,2.—pp.47-49], comprising an input data register and four neural units, each of them consists of a shift register, a weight coefficient register, eight multipliers, a multi-operand summation circuit and a block for the threshold function calculation.
Such neural processor executes weighted summation of fixed amount of input data for a fixed number of neurons in each clock cycle irrespective of the real range of input data values and their weight coefficients. In this case every input data as well as every weight coefficient are presented in the form of an operand with a fixed word length, determined by the bit length of the neural processor hardware units.
The closest one is neural processor [U.S. Pat. No. 5,278,945, U.S. C1. 395/27, 1994], comprising three registers, a multiplexer, a FIFO, a calculation unit to compute dot product of two vectors of programmable word length data with the addition of accumulated result and a nonlinear unit.
Input data vectors and their weight coefficients are applied to the inputs of such neural processor. In each clock cycle the neural processor performs weighted summation of several input data for one neuron by means of calculation the dot product of the input data vector by the weight coefficient vector. In addition the neural processor supports processing of vectors, which word length of separate elements may be selected from set of fixed values in program mode. With decreasing the word length of input data and weight coefficients their number in each vector increases and thus the neural processor performance improves. However, the word length of the obtained results is fixed and determined by the bit length of the neural processor hardware units.
A digital unit for saturation with saturation region, determined by absolute value of a number, is known [SU, No. 690477, Int. C1. G 06 F 7/38, 1979], comprising three registers, an adder, two code converters, two sign analyzing blocks, a correction block, two groups of AND gates and a group of OR gates. Such unit allows to calculate saturation functions for a vector with N input operands per 2N clock cycles.
The closest one is saturation unit [U.S. Pat. No. 5,644,519, U.S. C1. 364/736.02, 1997], comprising a multiplexer, a comparator and two indicators of the saturation. Such unit allows to calculate saturation functions for a vector with N input operands per N cycles.
A calculation unit is known [U.S. Pat. No. 5,278,945, U.S. C1. 395/27,1994], comprising multipliers, adders, registers, a multiplexer and a FIFO. Said unit allows to calculate dot product of two vectors, which contains M operands each, per one clock cycle and to multiply of a matrix containing N×M operands by a vector consisting of M operands per N cycles.
The closest one is calculation unit [U.S. Pat. No 4,825,401, U.S. C1. 364/760, 1989], comprising 3N/2 AND gates, N/2 decoders for decoding a multiplier on the basis of Booth's algorithm, a cell array of N columns by N/2 cells for multiplication, where each cell consists of a circuit to generate one bit of partial product on the basis of Booth's algorithm and of a one-bit adder, a 2N-bit adder, N/2 multiplexers, N/2 additional circuits to generate one bit of partial product on the basis of Booth's algorithm and N/2 implicators. Said unit allows to multiply two N-bit operands or to multiply element-by-element two vectors of two (N/2)-bit operands each per one clock cycle.
A unit for summation of vectors with programmable word length operands is known [U.S. Pat. No. 5,047,975, U.S. C1. 364/786, 1991], comprising adders and AND gates with inverted input.
The closest one is adder [U.S. Pat. No. 4,675,837, U.S. C1. 364/788, 1987], comprising a carry logic and in its every bit—a half-adder and an EXCLUSIVE OR gate. Said adder allows to add two vectors of N operands each per N cycles.
SUMMARY OF THE INVENTION
The neural processor comprises first, second, third, fourth, fifth and sixth registers, a shift register, an AND gate, first and second FIFOs, first and second saturation units, a calculation unit, incorporating inputs of first operand vector bits, inputs of second operand vector bits, inputs of third operand vector bits, inputs of data boundaries setting for first operand vectors and result vectors, inputs of data boundaries setting for second operand vectors, inputs of data boundaries setting for third operand vectors, first and second inputs of load control of third operand vectors into the first memory block, input of reload control of third operand matrix from the first memory block to the second memory block and outputs of bits of first and second summand vectors of results of the addition of first operand vector and product of the multiplication of second operand vector by third operand matrix, stored into the second memory block, an adder circuit, a switch from 3 to 2 and a multiplexer, and first data inputs of bits of the switch from 3 to 2, data inputs of the first FIFO, of first, second, third and fourth registers and parallel data inputs of the shift register are bit-by-bit coupled and connected to respective bits of first input bus of the neural processor, which each bit of second input bus is connected to second data input of the respective bit of the switch from 3 to 2, which first output of each bit is connected to input of the respective bit of input operand vector of the first saturation unit, which control input of every bit is connected to output of the corresponding bit of the second register, second output of each bit of the switch from 3 to 2 is connected to input of the respective bit of input operand vector of the second saturation unit, which control input of each bit is connected to output of respective bit of the third register, output of each bit of the first register is connected to first data input of the respective bit of the multiplexer, which second data input of each bit is connected to output of the respective bit of result vector of the first saturation unit, output of each bit of the multiplexer is connected to input of the respective bit of first operand vector of the calculation unit, which input of each bit of second operand vector is connected to output of the respective bit of result vector of the second saturation unit, data outputs of the first FIFO are connected to inputs of the respective bits of third operand vector of the calculation unit, which output of each bit of first summand vector of results of the addition of first operand vector and product of the multiplication of second operand vector by third operand matrix, stored into the second memory block, is connected to input of respective bit of first summand vector of the adder circuit, which input of each bit of second summand vector is connected to output of respective bit of second summand vector of results of the addition of first operand vector and product of the multiplication of second operand vector by third operand matrix, stored into the second memory block of the calculation unit, which each input of data boundaries setting for first operand vectors and result vectors is connected to output of the respective bit of the fifth register and to the respective input of data boundaries setting for summand vectors and sum vectors of the adder circuit, which output of each bit of sum vector is connected to respective data input of the second FIFO, which each data output is connected to the respective bit of output bus of the neural processor and to third input of the respective bit of the switch from 3 to 2, output of each bit of the fourth register is connected to data input of
Chernikov Vladimir Mikhailovich
Fomin Dmitriy Viktorovich
Shevchenko Pavel Aleksandrovich
Viksne Pavel Evgenjevich
Yafrakov Mikhail Fedorovich
Davis George B.
Joint-Stock Company Research Centre “Module”
Kenyon & Kenyon
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