Boots – shoes – and leggings
Patent
1991-04-26
1994-11-29
Coleman, Eric
Boots, shoes, and leggings
3642513, 3642595, 364251, 3642463, 364DIG1, 295425, G06F 1200
Patent
active
053697731
ABSTRACT:
A virtual-zero architecture is intended for use in a single instruction stream, multiple data stream (SIMD) processor which includes an input bus, an input unit, manipulation units, an output unit and an output bus. The virtual-zero architecture includes a memory unit (40) for storing data, an arithmetic unit (42) for mathematically operating on the data, a memory address generation unit (32) and an adder for computing a next memory address. The memory address generation unit (32) includes an address register (34) in the memory unit for identifying the address of a particular data block, a counter (38) for counting the number of memory addresses in a particular data block, and a rotation register (36) for providing a data-void address in the memory unit if and only if all of the entries in the data block are zero. The memory (40) and the address (32) units provide zero-value data blocks to the arithmetic unit (44) to simulate the data block having the data-void address during processing. The architecture may also be used to selectively handle input to a system.
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Adaptive Solutions, Inc.
Coleman Eric
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