Neural network, processor, and pattern recognition apparatus

Details Neural network, processor, and pattern recognition apparatus Neural network, processor, and pattern recognition apparatus

1993-02-17

1996-05-21

MacDonald, Allen R.

Boots, shoes, and leggings

395 27, 364DIG2, G06F 1518

Patent

active

055198112

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to improvements in neural networks, hardware for carrying out the functions of a neural network, neural network processors, and neural network pattern recognition apparatuses.
2. Description of the Related Art
A neural network, namely, a system of recognizing predetermined input information and providing the results of the recognition which is, based on a conception entirely differing from those on which conventional methods are based, has been developed and applied to various fields. The neural network is a model of a human brain, which can be realized in various ways.
A neural network has been proposed in a mathematical algorithm having a complex structure. Accordingly, conventional neural networks have been realized by computer simulation. Computer simulation, however, operates at a comparatively low processing speed, which is a problem in some practical applications. Recently, a comprehensive study of the neural network has been made and pieces of hardware for realizing neural networks have been proposed. However, the proposed hardware deals with neural networks having only one or two layers.
A Neocognitron is one model of a neural network. Only a few studies have been made on the development of hardware for realizing a Neocognitron, since a Neocognitron is a neural network having a complex structure. Hardware for realizing a Neocognitron has been reported in a paper published by MIT. This paper was published in the poster session the NIPS (Neural Information Processing & Systems) '90 conference. The hardware is simple in structure comprising, in combination, 143 CCD arrays and seven MDACs (multiplier DA converters). Most circuits employed in the hardware are digital circuits. Basically, both input data and coefficient data are stored in the digital circuits, and the semianalog MDACs carry out multiplication. The method of fabricating this system, however, has not been able to fabricate division circuits satisfactorily to date only first layer has been realized. This hardware has a small degree namely, integration of seven multipliers in 29 MM.sup.2.
The realization of such a neural network in hardware has encountered many difficulties and hence methods have been studied for the high-speed simulation of a neural network having three or more layers. One of the methods simulates a neural network using a program executed by parallel processing computers. However, if this method is employed, it often occurs that the computational topology of the neural network does not coincide with the architecture of each computer which reduces the efficiency of data transmission between the processing elements. Even if parallel computers having many processing elements are employed for high-speed simulation, it is difficult to improve the cost performance.


SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide techniques capable of realizing a neural network of a complex structure, such as Neocognitron, in hardware.
A neural network processor in accordance with the present invention realizing a feed-forward neural network having a multilayer structure comprises a plurality of processing elements respectively corresponding to the neurons of the neural network, wherein the processing elements are MOS analog circuits forming a systolic array and dealing with input and output variables represented as voltages.
In this feed-forward neural network, all of the component neurons of the neural network receive input signals from the previous layer in a normal operating mode, except for signal transmission in a learning mode, such as back propagation signals are never transmitted from the succeeding layer to the previous layer or between the neurons in the same layer.
Preferably, the neural network processor in accordance with the present invention is a neural network processor realizing a Neocognitron.
Preferably, each MOS analog circuit of the neural network processor in accordance with the present invention

REFERENCES:
patent: 5083285 (1992-01-01), Shima et al.
patent: 5091864 (1992-02-01), Baji et al.
patent: 5138695 (1992-08-01), Means et al.
Programmable Analog Vector-Matrix Multipliers Francis Kub et al. IEEE Feb. 1990.
VLSI Design of Compact and High-Precision Analog Neurat Network Processors Choi et al. IEEE 7-11 Jun. 1992.
A Massively Parallel and Highly Pipelined VLSI Analog Neocognitron Image Processor Yoneda et al. IEEE 10-13 May 1992.
An Analog Cell Library Useful for Ann Zhong et al., IEEE 1-4 Apr. 1990.
A Massively Parallel and Highly Pipelined VLSI Analog Neo Cognitron Image Processor. Yoneda, Thesis Aug. 1991.
"A CCD Programmable Image Processor and Its Neural Network Applications," Chiang, Alice M. and Chuang, Michael L. J. Solid-State Circuits, vol. 26, No. 12, pp. 1894-1901, Dec. 1991

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