Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2001-12-07
2003-06-24
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S099000
Reexamination Certificate
active
06583651
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to neural network output selector devices, and more specifically to a device and method for selecting within a group of analog signals the one with the lowest or with the highest value.
2. Description of the Related Art
As known, the majority of these devices, which are known in the literature as “Winner Take All” (WTA) circuits or as “Loser Take All” (LTA) circuits, are provided by means of architectures which exhibit a voltage-follower configuration and make use of inhibitor mechanisms operating among the calculation elements included in them.
A first known technical solution is described in the article “Winner Take All Networks of O(N) Complexity,” J. Lazzaro et al.,
Neural Inform Proc. Syst.
1:703-711, Denver, Colo., 1989, and calls for the use of a selector device comprising a plurality of circuit branches operating in parallel and each including a first voltage follower transistor T
1
i
and a second local positive feedback transistor T
2
i,
where i=1, . . . j, . . . n. The device also comprises a total feedback line LN common to all the circuit branches. Operation of the selector device is as follows. Each circuit branch receives the input of a one-way current Ii and supplies output of a voltage Vi which represents the result of the selection process. When the current Ii=max (I
1
, . . . In), the voltage Vi coincides with a logarithmic function of Ii, and if the current Ij<<Ii, the voltage Vj~0. Although advantageous in some ways, this first solution exhibits diverse shortcomings. Indeed, the device does not provide any offset compensation and has a calculation time which depends on the number of elements making it up.
A second known technical solution is described in the article “A Scalable High-Speed Current-Mode Winner Take All Network for VLSI Neural Applications,” Sean Smedley et al.,
IEEE Transactions on Circuits and Systems-
I:
Fundamental Theory and Applications
42(5), 1995 which proposes a tree-structured circuit comprising a plurality of cells provided by using bipolar transistors integrated with a BICMOS technology. Each cell receives at input two current signals I
1
and I
2
which are compared with each other to select the highest one. The latter represents the input for a cell included in a subsequent layer of the tree structure and so on until there is obtained at output the higher input current signal.
A third technical solution is disclosed in U.S. Pat. No. 5,905,387 (“the '387 patent”) issued on May 18, 1999, to Chinosi, et al, and entitled “ANALOG VOLTAGE-SIGNAL SELECTOR DEVICE”, the disclosure of which is incorporated herein by reference. Chinosi's approach has significant advantages in speed and flexibility. A circuit which has improved speed and power consumption characteristics beyond those of the '387 patent is preferred.
BRIEF SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, the output-selector employs a differential amplifier configuration with a plurality of analog voltage inputs and an analog comparison voltage input. The output selector also employs a logic circuit. The output-selector determines which of the plurality of analog input voltages has the lowest potential. In another aspect of the present invention, the output-selector determines which of the plurality of analog input voltages has the highest potential.
REFERENCES:
patent: 5408194 (1995-04-01), Steinbach et al.
patent: 5905387 (1999-05-01), Chinosi et al.
patent: 6032140 (2000-02-01), Fabbrizio et al.
Lazzaro, J. et al., “Winner-Take-All Networks of O(N) Complexity,”Neural Inform Proc. Syst., vol. 1, pp. 703-711, Denver, CO, 1989.
Smedley, S. et al., “A Scalable High-Speed Current-Mode Winner-Take-All Network for VLSI Neural Applications,”IEEE Trans. on Circuits and Systems-I: Fundamental Theory and Applications, 42(5), 1995.
McCreary, J. et al., “NMOS Comparator for a Bubble Memory,”in Proceedings of the IEEE International Solid-State Circuits Conference, Session XIV: Analog Techniques, Feb. 19, 1981, pp. 184-185, 271.
Carlson David V.
Jorgenson Lisa K.
STMicroelectronics Inc.
Wells Kenneth B.
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