Patent
1993-11-23
1995-09-19
Downs, Robert W.
395 21, 395 23, G06F 1500
Patent
active
054524024
ABSTRACT:
In a multi-layered neural network circuit provided with an input layer having input vectors, an intermediate layer having networks in tree-like structure whose outputs are necessarily determined by the values of the input vectors and whose number corresponds to the number of the input vectors of the input layer, and an output layer having plural output units for integrating all outputs of the intermediate layer, provided are learning-time memories for memorizing the numbers of times at learning in paths between the intermediate layer and the respective output units, threshold processing circuits for threshold-processing the outputs of the leaning-time memories, and connection control circuits to be controlled by the outputs of the threshold processing circuits for controlling connection of paths between the intermediate layer and the output units. The outputs of the intermediate layer connected by the connection control circuits are summed in each output unit. Thus, the neural network circuit for recognizing an image or the like can execute recognition and learning of data to be recognized at high speed with small circuit size, and the recognition accuracy for unlearned data is high.
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Kouda Toshiyuki
Maruno Susumu
Maruyama Masakatsu
Nakahira Hiroyuki
Sakiyama Shiro
Downs Robert W.
Hafiz Tarig
Matsushita Electric - Industrial Co., Ltd.
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