Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1999-02-26
2001-03-06
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S136000
Reexamination Certificate
active
06198421
ABSTRACT:
BACKGROUND
(1) Field of the Invention
This invention relates generally to the field of analog to digital converters. More particularly, this invention relates to neural analog to digital converters.
(2) Background Information
Most sensing devices such as temperature, pressure, level or flow rate sensors, yield signals which are analog in nature. Usually, these analog signals are continuous over some normally pre-determined range. These signals are transformed to digital or discrete signals to use digital computing devices to process these signals. The process of converting analog signals into corresponding digital signals is known as analog-to-digital conversion and the circuits or devices used to perform this conversion are called Analog-to-Digital Converters (ADC).
There has been increasing interest in the design of ADC based on neural networks. Artificial neural network (ANN, commonly just “neural network” or “neural net”) conventionally may be viewed as a network of many very simple processors (“units” or “neurons”), each possibly having a (small amount of) local memory. The processors may be connected by unidirectional communication channels (“connections”), which carry numeric (as opposed to symbolic) data. The processors conventionally may operate only on their local data and on the inputs they receive via the connections. In this regard, a neural network may be a processing device, either an algorithm, or actual hardware, whose design may have been inspired by the design and functioning of animal brains and components thereof.
As an artificial intelligence, most conventional neural networks have some sort of “training” rule whereby the weights of connections are adjusted on the basis of presented patterns. In other words, neural networks “learn” from examples, just like children learn to recognize dogs from examples of dogs, and exhibit some structural capability for generalization.
Neurons are often elementary non-linear signal processors (in the limit they may be simple threshold discriminators). Another feature of neural networks that may distinguish them from other computing devices is a high degree of interconnection that allows a high degree of parallelism. Further, there is no idle memory containing data and programs, but rather each neuron may be pre-programmed and continuously active. The term “neural net” logically may include biological neural networks, whose elementary structures conventionally are far more complicated than the mathematical models used for neural networks.
In regards to Analog-to-Digital converters, one such neural ADC was proposed by Hopfield and Tank in the reference, “Simple Neural Optimization Networks: An A/D Converter Signal Decision Circuit and Linear Programming Circuit.”
IEEE TRANS. On Circuits and Systems.
Vol. CAS-38 No. 5, May 1986, pp 533-541. This ADC is formulated as an optimization problem. Due to the recurrent structure of the ADC, the output of the ADC is plagued by a local minima problem. It is desirable to provide a neural ADC that is manufacturable, robust, process tolerant, fast responding and that consumes less power than conventional neural ADCs.
SUMMARY OF THE INVENTION
One embodiment of the present invention includes a flash analog-to-digital converter (ADC). The ADC includes a plurality of N stages to provide N digital signals. The plurality of N stages includes a first stage to provide a sum of an input current, related to a voltage to be converted, and of a reference current. The first stage provides a first digital signal in one of first and second states if the sum has one of first and second signs, respectively. The plurality of N stages further includes i stages, with i=2 . . . N. Each stage i includes an output circuit and 2
(i−2)
sub-stages coupled to the output circuit. Each sub-stage includes an input and a hidden circuit coupled therebetween. The input circuit is configured to provide a first sum of the input current and of a first reference current. Each hidden circuit provides to the output circuit a second reference current when the first sum has a first sign. The output circuit generates an i
th
digital signal in one of a first and second states when a second sum of the input current and of the second reference current has one of first and second signs respectively.
REFERENCES:
patent: 4647904 (1987-03-01), Kuklewicz
patent: 4965579 (1990-10-01), Liu et al.
patent: 5675341 (1997-10-01), Vallancourt et al.
patent: 5815107 (1998-09-01), Frankeny et al.
Doyle James T.
Liepold Carl F.
Blakely , Sokoloff, Taylor & Zafman LLP
Intle Corporation
Williams Howard L.
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