Network with data rate adjustment for virtual circuits with asyn

Details Network with data rate adjustment for virtual circuits with asyn Network with data rate adjustment for virtual circuits with asyn

1993-08-05

1997-04-01

Marcelo, Melvin

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370395, 370416, 370468, H04L 1256

Patent

active

056174160

ABSTRACT:
An ATM network including a plurality of channels comprises a cell memory MC comprising r buffers for virtual circuits (MC1, . . . , MC2). The output cells of MC carried by a multiplex DNO are read by a readout address section circuit. The circuit also comprises a mechanism for establishing a one-to-one relationship between each activated channel and a predetermined level of priority, a rhythm synthesis table, a mechanism dependent on the output of the rhythm table for activating pulse signals which have frequencies that correspond to the data rates of activated channels, an automatic timing unit and a mechanism for selecting a channel of highest priority at each cell time.

REFERENCES:
patent: 5189672 (1993-02-01), Le Bihan
patent: 5287347 (1994-02-01), Spanke

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