Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
1999-07-29
2003-05-20
Ton, Dang (Department: 2666)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C370S509000, C370S510000, C370S512000
Reexamination Certificate
active
06567422
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a network synchronization controller and a timing loop prevention method. More particularly, the present invention relates to a controller which establishes timing synchronization within a network, and to a method of preventing the occurrence of a timing loop within a network.
2. Description of the Related Art
Today's digital telecommunications systems exploit various data multiplexing techniques to fully utilize the available transmission bandwidth and provide economical data transport services. Synchronous Digital Hierarchy (SDH) is a typical digital transmission architecture with highly sophisticated multiplexing facilities. SDH offers various high-speed data services, as well as defining multiplexing methods to interface with existing low-speed telecommunication services. This ITU-T standard technology is accepted as a next-generation data communications infrastructure, and many practical systems are being developed.
According to the concept of SDH, all network elements (NEs) within a network must operate exactly in synchronization with each other. To this end, the network provides a single reference timing source, or clock, with a predefined frequency and required accuracy. Such a reference clock signal is distributed over the network, allowing each network element to keep its local timing system synchronized with the reference timing. To ensure the establishment of network synchronization, some conventional systems use a synchronization status message byte (SSMB) defined as part of SDH section overhead. SSMB is actually a four-bit data field allocated in the lower half of S
1
byte, which indicates the quality level of a clock signal being used. The timing distribution path in an SDH network is established and maintained by using an SSMB-based synchronization messaging mechanism.
FIG. 14
shows an example of timing distribution in a conventional SDH network. This SDH network
200
involves four network elements NEa to NEd interconnected in a ring topology. On the top of the ring, the network element NEa is directly coupled to a reference timing source CLK
1
, and its operation is synchronized with it. This reference clock signal CLK
1
is distributed over the ring in the counter-clockwise direction, thus forming a timing distribution path of (NEa→NEb→NEc→NEd). All the network elements NEa to NEd on this path are timed by the reference clock signal CLK
1
.
The timing distribution path may not be permanent, but can be reconfigured, if required. In case of a ring failure, for example, each network element switches its clock signal sources according to the clock quality status information provided in the form of SSMB, trying to reestablish the network synchronization.
The above-described conventional system, however, has a problem in that its messaging mechanism lacks detailed information that is required to reestablish the network synchronization, and thus cannot avoid the occurrence of an unwanted timing loop.
FIG. 15
illustrates a timing loop created in the conventional SDH network
200
of FIG.
14
. It is assumed that a ring failure has occurred between two network elements NEa and NEb. Because the reference clock signal CLK
1
from NEa is disrupted, NEb now chooses another clock signal supplied from NEc in an attempt to synchronize itself with that signal. NEc, on the other hand, uses a clock signal supplied from NEb for synchronization, meaning that the network element NEc operates at the timing that derives from NEc itself. The last network element NEd is then timed by a clock signal supplied from NEc. This results in a timing loop produced in the SDH network
200
, where NEb, NEc, and NEd operate in synchronization with each other, but no qualified reference timing such as CLK
1
is present.
As explained above, network elements in a conventional network switch reference timing signals without considering their origins. This is because of the lack of detailed information regarding the sources of clock signals and the like, which is necessary for reliable network synchronization. As a result, some network elements happen to choose a clock signal that is derived from themselves, making a timing loop.
A timing loop disrupts the synchronization within a network and makes it difficult for the network to recover from failure by itself. It also affects the performance of a network, causing jitter (short-term phase variations) and wander (long-term phase variations including seasonal changes). Accordingly, there is a demand for a robust network synchronization method which avoids the occurrence of unwanted timing loops, as well as being free from variations in clock frequencies and phases.
SUMMARY OF THE INVENTION
Taking the above into consideration, an object of the present invention is to provide a network synchronization controller which prevents the occurrence of a timing loop in a more effective and efficient manner.
To accomplish the above object, according to the present invention, there is provided a network synchronization controller which controls a process of establishing timing synchronization within a network. This network synchronization controller comprises a clock status message controller, disposed in each network element on the network, which produces and sends a clock status message composed of clock quality data and synchronization control data. The clock quality data indicates the quality level of a clock signal that the each network element supplies to its neighboring network element, while the synchronization control data includes information to be used to make the network synchronized with a single reference timing source. The controller further comprises a clock selector, disposed in each network element, which selects one of the clock signals that each network element receives, based on the clock status messages received along with the clock signals.
It is another object of the present invention to provide a method of preventing the occurrence of a timing loop in a more effective and efficient manner.
To accomplish this second object, according to the present invention, there is provided a method of preventing a network from forming a timing loop. This method comprises the steps of: (a) producing a clock status message composed of clock quality data and synchronization control data and sending the clock status message, together with a clock signal being selected, from each network element to a neighboring network element thereof; and (b) selecting one of the clock signals received from other network elements, based on the clock status messages received along with the clock signals. Here, the clock quality data indicates the quality level of the clock signal, and the synchronization control data includes information to be used to establish network synchronization.
REFERENCES:
patent: 5886996 (1999-03-01), Wolf
patent: 6185216 (2001-02-01), Chapman
patent: 5-056023 (1993-03-01), None
patent: 7-2355918 (1995-09-01), None
patent: 9-064842 (1997-03-01), None
patent: 9-219687 (1997-08-01), None
patent: 10-093519 (1998-04-01), None
patent: 10-145321 (1998-05-01), None
Mizukura Ken
Morita Hirotaka
Moriya Ryuichi
Rikitake Nobuhiro
Takeguchi Koji
Katten Muchin Zavis Roseman
Ton Dang
Vu Thong N.
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