Network switching system including a zero-delay output buffer

Details Network switching system including a zero-delay output buffer Network switching system including a zero-delay output buffer

1997-06-16

1999-01-12

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327159, 327147, 327150, H03L 700

Patent

active

058595503

ABSTRACT:
A zero-delay buffer circuit includes a modified phase-locked loop (PLL) circuit configured to minimize clock skew among data output buffers of modules within a high-speed network switch system. Each module includes an application-specific integrated circuit (ASIC) chip that contains the modified PLL circuit; circuitry inserted within a feedback loop of the PLL is representative of a clock distribution tree that is common to the output buffers of the chip. The absolute delay of that tree typically differs among the ASICs because of process, voltage and temperature variations within the system. The circuitry inserted within the feedback loop effectively compensates for the absolute delay of the common distribution tree circuit components.

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