Network switching system having overflow bypass in internal...

Details Network switching system having overflow bypass in internal... Network switching system having overflow bypass in internal...

1999-01-27

2002-10-08

Kizou, Hassan (Department: 2738)

Multiplex communications

Fault recovery

Bypass an inoperative switch or inoperative element of a...

C370S414000, C370S428000, C370S429000

Reexamination Certificate

active

06463032

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to data communication systems, and more particularly, to a system for preventing loss of data due to overflow conditions in a network switching system.
BACKGROUND ART
A multiport switch may be provided in a data communication network to enable data communication between multiple network stations connected to various ports of the switch. A logical connection may be created between receive ports and transmit ports of the switch to forward received frames to appropriate destinations. Based on frame header information, a decision making engine selectively controls forwarding of received frames to a destination station.
To prevent loss of data due to overflow conditions, it would be convenient to provide the decision making engine with an overflow mechanism that creates a bypass for overflow data.
DISCLOSURE OF THE INVENTION
The invention provides a novel method of overflow data handling in a multiport data switching system having a decision making engine for controlling data forwarding between receive ports and at least one transmit port. Data blocks representing received data packets are placed in data queues corresponding to the receive ports. The data queues are transferred to logic circuitry for processing in accordance with a predetermined algorithm. Then, a forwarding decision is made to determine the at least one transmit port. An overflow bypass is provided to allow at least a portion of a data block to bypass the logic circuitry, when at least one of the data queues is in an overflow state.
In accordance with one aspect of the invention. each data block includes a pointer for indicating a memory location for storing the received data packet. The pointers are allowed to bypass the logic circuitry when the overflow state is detected.
Preferably, overflow data is buffered in overflow registers allocated to the receive ports. When the overflow state is detected, the overflow data is placed in a first section of the corresponding overflow register. The overflow data is transferred from the first section to a second section of the overflow register when the end of a data packet represented by the overflow data is detected.
In accordance with another aspect of the invention, the decision making engine includes a plurality of queuing devices corresponding to the plurality of the receive ports for queuing data blocks representing the data packets received by the corresponding receive ports. Logic circuitry is responsive to the plurality of queuing devices for processing the data blocks in accordance with a predetermined algorithm. A forwarding circuit is responsive to the logic circuitry for identifying the selected transmit port for each data packet. An overflow handling circuit provides an overflow bypass for bypassing the logic circuitry to transfer at least a portion of a data block representing received data packet directly to the forwarding circuit when at least one of the plurality of the queuing devices is in an overflow state.
In accordance with a preferred embodiment of the invention, the overflow handling circuit comprises at least one arbitrator for performing arbitration between requests for access to the forwarding circuit for the plurality of overflow registers. The receive ports may include regular ports, at least one high-speed port for receiving data packets at a rate higher than a rate at the regular ports, and at least one expansion port for receiving data packets from other communication systems. The requests for access to the forwarding circuit for the overflow registers allocated to the high-speed and expansion ports may have a higher priority than requests for access to the forwarding circuit for the overflow registers allocated to the regular ports. The overflow handling circuit may comprise a first arbitrator for performing arbitration between requests for access to the forwarding circuit for the overflow registers allocated to the regular ports, and a second arbitrator for performing arbitration between requests for access to the forwarding circuit for the overflow registers allocated to the high-speed and expansion ports. In response to a request for access to the forwarding circuit for a given overflow register, each arbitrator produces a grant signal for enabling the forwarding circuit to receive the data from that overflow register.
Various objects and features of the present invention will become more readily apparent to those skilled in the art from the following description of a specific embodiment thereof, especially when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5515376 (1996-05-01), Murphy et al.
patent: 5603064 (1997-02-01), Bennett
patent: 6185630 (2001-02-01), Simmons
patent: 6192028 (2001-02-01), Simmons et al.
patent: 6233244 (2001-05-01), Runaldue et al.

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