Network switching architecture utilizing cell based and packet b

Details Network switching architecture utilizing cell based and packet b Network switching architecture utilizing cell based and packet b

1999-06-30

2000-11-28

Cangialosi, Salvatore

Multiplex communications

Data flow congestion prevention or control

Using antijabber circuit

370395, H04L 1228, H04L 1266

Patent

active

061544469

ABSTRACT:
A network switch for network communications includes a first data port interface which supports a plurality of data ports which transmit and receive data at a first data rate. A second data port interface is provided; the second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. An internal memory is provided, and communicates with the first data port interface and the second data port interface. A memory management unit is provided, and includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A communication channel is provided, with the communication channel communicating data and messaging information between the at least one first data port interface, the at least one second data port interface, the internal memory, and the memory management unit. One data port interface of the first data port interface and the second data port interface includes a head-of-line blocking prevention mechanism. The head-of-line blocking prevention mechanism includes a determination unit for determining when head-of-line blocking is occurring based upon cell based and packet based thresholds.

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patent: 5831980 (1998-11-01), Varma et al.
patent: 5856975 (1999-01-01), Rostoker et al.
patent: 5856977 (1999-01-01), Yang et al.
patent: 5898687 (1999-04-01), Harriman et al.
patent: 5918074 (1999-06-01), Wright et al.
patent: 5923656 (1999-07-01), Duan et al.

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