Network switch with a parallel shared memory

Details Network switch with a parallel shared memory Network switch with a parallel shared memory

2001-08-24

2008-09-02

Backer, Firmin (Department: 2616)

Multiplex communications

Pathfinding or routing

Through a circuit switch

C370S390000, C370S429000

Reexamination Certificate

active

07420969

ABSTRACT:
A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices. A selected intermediate layer circuit of the set of intermediate layer circuits receives the selected cell and assigns the selected cell to a selected buffer corresponding to the selected destination device. An output layer includes a set of output layer circuits corresponding to the set of destination devices. A selected output layer circuit of the set of output layer circuits stores the selected cell prior to routing the selected cell to a selected output layer circuit output node.

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Sundar Iyer, et al.; “Analysis of a Packet Switch with Memories Running Slower than the Line-Rate”; Computer Systems Laboratory, Stanford University, Stanford, CA 94305-9030; 9 pages.
Sundar Iyer; “Analysis of a Packet Switch with Memories Running Slower than the Line Rate”; © Copyright 2000 by Sundar Iyer; pp. 1-47.

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