Network rearrangement method and system

Details Network rearrangement method and system Network rearrangement method and system

1989-04-10

1994-02-15

Baker, Stephen M.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340827, 364DIG1, 3642687, 371 112, G06F 1120, G06F 1336

Patent

active

052874915

ABSTRACT:
A system and method for a fault-tolerant system for parallel networks which interconnect processors and the first of the parallel networks distributed in an Omega configuration and the second of the parallel networks distributed in a reversed Omega configuration.

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Castan, M., et al., "MaRS:A parallel graph reduction multiprocessor", Computer Architecture News, vol. 16, No. 3, Jun. 1988, pp. 17-24.
Contessa, A., "An approach to fault tolerance and error recovery in a parallel graph reduction machine:MaRS-a case study", Computer Architecture News, vol. 16, No. 3, Jun. 1988, pp. 25-32.
H. J. Siegel, W. T. -Y. Hsu, M. Jeng, "An Introduction to the Multistage Cube family of Interconnection Networks," Journal of Supercomputing, 1, 13-42(1987).
C. -L. Wu and T. -Y. Feng, "On A Class of Multistage Interconnection Networks," IEEE Transactions on computers, vol. C-29, No. 8, pp. 694-702, Aug. 1980.

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