Network packet buffer allocation optimization in memory bank...

Details Network packet buffer allocation optimization in memory bank... Network packet buffer allocation optimization in memory bank...

2007-01-02

2007-01-02

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C710S052000, C710S056000

Reexamination Certificate

active

11092010

ABSTRACT:
An arrangement of buffer in a memory unit including a plurality of memory banks may store information in rows that span the memory banks. Moreover, a processor may be adapted to (i) establish a plurality of buffers to be associated with the memory unit, wherein the size of each buffer is less than the width of a memory bank, and (ii) arrange for a selected buffer to begin in a memory bank other than a memory bank in which a previously selected buffer begins.

REFERENCES:
patent: 5768546 (1998-06-01), Kwon
patent: 5946293 (1999-08-01), Beale et al.
patent: 6799200 (2004-09-01), Blackmore et al.
patent: 6801958 (2004-10-01), Gugel

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