Network on chip with partitions

Details Network on chip with partitions Network on chip with partitions

2011-01-18

2011-01-18

Meky, Moustafa M (Department: 2457)

Electrical computers and digital processing systems: multicomput

Multicomputer data transferring via shared memory

Partitioned shared memory

C711S141000

Reexamination Certificate

active

07873701

ABSTRACT:
A design structure embodied in a machine readable medium is provided. Embodiments of the design structure include a network on chip (‘NOC’), the NOC comprising: integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers; the network organized into partitions, each partition including at least one IP block, each partition assigned exclusive access to a separate physical memory address space; and one or more applications executing on one or more of the partitions.

REFERENCES:
patent: 6668308 (2003-12-01), Barroso et al.
patent: 6988170 (2006-01-01), Barroso et al.
patent: 7254603 (2007-08-01), Weber et al.
patent: 7356633 (2008-04-01), Weber et al.
patent: 7603441 (2009-10-01), Synek et al.
patent: 7660932 (2010-02-01), Chou et al.

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