Network intermediate system with message passing architecture

Details Network intermediate system with message passing architecture Network intermediate system with message passing architecture

1995-05-10

1997-01-07

Barry, Lance Leonard

39520013, 39520015, 395877, 395309, 3952002, G06F 1300, G06F 15163

Patent

active

055926223

ABSTRACT:
A system uses a message passing paradigm for transferring large amounts of input/output data among a plurality of processors, such as a network intermediate system or router. A bus interconnects the plurality of processors with a plurality of bus interface devices. The bus interface device which originates a transfer includes a command list storing lists of commands which characterize transfers of data messages from local memory across the bus and a packing buffer which buffers the data subject of the command being executed between local memory and the bus. A bus interface device which receives a transfer includes a free buffer list storing pointers to free buffers in local memory into which the data may be loaded from the bus, and a receive list storing pointers to buffers in local memory loaded with data from the bus. The command list includes a first high priority command list and a second lower priority command list for managing latency of the higher priority commands in the software of the processor. The bus interface which receives the transfer includes control logic which manages data transfer into and out of an inbound buffer, including receiving burst transfers of message transfer cells from the bus, loading free buffers in local memory from the inbound buffer with message transtar cells, and updating the receive list. The receive list includes a first higher priority receive list and a second lower priority receive list for reliability management, and logic which monitors the free list so that lower priority messages may be dropped to prevent overflow of free buffer resources.

REFERENCES:
patent: 4475155 (1984-10-01), Oishi et al.
patent: 4783730 (1988-11-01), Fischer
patent: 4860244 (1984-08-01), Bruckert et al.
patent: 4912723 (1990-03-01), Verbanets, Jr.
patent: 4962497 (1990-10-01), Ferenc et al.
patent: 5088090 (1992-02-01), Yacoby
patent: 5093824 (1992-03-01), Coan et al.
patent: 5109484 (1992-04-01), Hughes et al.
patent: 5121383 (1992-06-01), Golestani
patent: 5131081 (1992-07-01), MacKenna et al.
patent: 5134691 (1992-07-01), Elms
patent: 5255387 (1993-10-01), Arnold et al.
patent: 5335325 (1994-08-01), Frank et al.
patent: 5379296 (1995-01-01), Johnson et al.
patent: 5404524 (1995-04-01), Celi, Jr.
patent: 5469548 (1995-11-01), Callison et al.
patent: 5485455 (1996-01-01), Dobbins et al.
patent: 5521910 (1996-05-01), Matthews
Lynn Choi and Andrew Chien, Integrating Networks and Memory Hierarchies in a Multicomputer Node Architecture in IEEE 1994 Parallel Processing Symposium, pp. 10-17 (1994).

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