Patent
1995-12-21
1998-03-10
Harrell, Robert B.
G06F 13372
Patent
active
057271496
ABSTRACT:
A network interface apparatus connected between a LAN adaptor possessed by a computer and a transceiver provided on a network includes a buffer memory for storing data, a first control circuit for communicating with the LAN adaptor, a second control circuit for communicating with the transceiver, and a processor for controlling the first and second control circuits to control the transfer of data between the LAN adaptor and the transceiver. The processor causes the buffer memory to store transmit data transmitted from the LAN adaptor and transmits the stored transmit data in the buffer memory to the transceiver in a transmission time zone which is allotted beforehand. The transmission time zone is determined by the processor on the basis of the reception of a synchronizing packet which is transferred on the network. Receive data received from the transceiver is selected by the processor so that only the selected receive data is sent to the LAN adaptor. A reference for the selection may include a protocol type, a port number on TCP/IP or the like.
REFERENCES:
patent: 5544324 (1996-08-01), Eden et al.
patent: 5650997 (1997-07-01), Yang et al.
Hirata Tetsuhiko
Koizumi Minoru
Takada Osamu
Wataya Hiroshi
Yanagisawa Emiko
Harrell Robert B.
Hitachi , Ltd.
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