Network for decreasing transmit link layer core speed

Details Network for decreasing transmit link layer core speed Network for decreasing transmit link layer core speed

2007-08-07

2007-08-07

Flynn, Nathan J. (Department: 2154)

Electrical computers and digital processing systems: multicomput

Network-to-computer interfacing

C709S233000, C709S234000, C710S051000, C710S052000, C710S060000, C710S071000, C710S072000

Reexamination Certificate

active

09816967

ABSTRACT:
A processor includes a core for providing speed reduction in communications between a transmission media and a processor having an upper link layer in a parallel-serial architecture. The core includes a lower logic layer, serial lanes connecting the logic layer to the transmission media, at least one selector connected to the serial lanes for supporting at least two differing data widths. The logic layer controls the selector, and multiple buffers are interposed in the serial lanes. The selector enables the speed reductions is the upper link layer of the processor. The processor is particularly applicable to interface components used in InfiniBand-type hardware.

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