Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-05-08
2001-03-27
Ton, Dang (Department: 2731)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
Reexamination Certificate
active
06208648
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates to a synchronous transmission system, to a network element and to an input/output device.
2. Discussion of Related Art
A synchronous transmission system is, for example, a transmission system for the Synchronous Digital Hierarchy (SDH system). In a SDH system, the signals to be transmitted are combined according to a predetermined pattern and structured in the form of frames. Such a frame is referred to as a synchronous transport module STM-N as described, for example, in the ITU-T recommendation “Recommendation G.707 (Draft) (November, 1995)”, e.g. in Chapter 7“Multiplexing Method.” In the frame, there is defined a section for control data, i.e. for “Section Overhead SDH” and “AU-n pointer”, and a section for message data, i.e. for a “Payload.” An overview of the Synchronous Digital Hierarchy is shown in Chapter 40 at pages 554-566 of “The Communications Handbook” edited by Jerry D. Gibson, CRC Press 1997. Also in the same volume in Chapter 39 is described the Synchronous Optical Network (SONET) at pages 542-553. The major differences between SDH and SONET are the terminology and the basic line rates used but the fundamental principles are the same. Therefore, it will be understood that even though most of the discussion and disclosure which follows is in terms of an SDH system, such is applicable to a SONET system as well, but using different terminology and basic line rates.
The SDH system is built up from a number of network nodes which are connected to each other via physical transmission media (e.g., optical fibers, coaxial cables). The network nodes usually consist of groups of individual network elements (e.g., add/drop multiplexers, cross-connects) which are set up to perform various specified functions. The CCITT recommendation “Recommendation G.783”, Chapter 2“Transport Terminal Functions”, defines the network elements in accordance with basic functions which include, among others, interface functions, monitoring functions and interconnect functions. An interface device provides the interface function for interfacing with the physical transmission medium. In the receive direction, an interface device (SPI, SDH Physical Interface) is capable of recovering the timing signal from the receive signal and recognizing a signal loss (LOS, Loss of Signal), thereby providing the signals LOS, DATA and TIMING (see G.783, FIG.
2
.
2
). In the transmit direction, the interface device is capable of transmitting, among others, a signal using the system timing signal.
The interface devices are generally implemented by combining optical transmit and receive modules and standard components (e.g. TDC2302C from Texas Instruments) or ASIC'S. A standard component of this type has, among others, the following functions: It transmits and receives STM-1 (called STS-3 (electrical)/OC-3 (optical) in SONET) signals with a bit rate of 155.52 Mbits/s. It recognizes the frame of the incoming signal and transmits a Frame Indication Signal. It also provides markers for the states Loss of Signal (LOS) and Loss of Frame (LOF).
Thereafter, the received STM-1 signal is processed further in a signal processing device which is also a standard component (e.g. TDC3003 from Texas Instruments) or an ASIC. This standard component has, among others, the following functions: It has to process the entire overhead. For signals which have been received and for signals which are to be transmitted, the standard component generates, in accordance with an external timing signal, pointers and performs pointer actions. The standard component also performs monitoring functions for the B1, B2 and B3 encoding, for error messaging (Far End Block Error, FEBE) and for counting the pointer actions.
The interface device and the signal processing device form an input/output device which interconnects to other components of the network element, for example with a switching matrix in a cross connect.
Since the network elements have become increasingly more complex and more densely integrated, the complexity of the circuitry and the number of gates of ASIC's has also increased. Consequently, more complex simulations and tests are necessary, resulting in still longer simulation and test times.
SUMMARY OF INVENTION
It is an object of the invention to provide a synchronous transmission system and a network element for a synchronous transmission system wherein the increasingly complex demands are satisfied in a simple manner.
In accord with a first aspect of the invention, a synchronous transmission system for digital signals combined to a multiplex signal, comprising network elements which are connected to each other via one or several transmission media, each network element further comprising an input/output device for receiving and transmitting the multiplex signal, with the input/output device further comprising an interface device and a signal processing device for processing data received from the interface device, is characterized in that the signal processing device comprises memory means for storing the data and a programmable processor, that the memory means is responsive to data and write address signals for arranging the data in a predetermined pattern for access by the processor for processing the data, and that the memory means is responsive to read address signals for conveying to the interface device data received from the processor.
According to a second aspect of the present invention, a network element for a synchronous transmission system, with an input/output device comprising an interface device capable of transmitting a multiplex signal and processing a received multiplex signal, and a signal processing device for processing data received from the interface device, is characterized in that the signal processing device comprises memory means for storing the data and a processor, that the memory means is responsive to data and write address signals for arranging the data in a predetermined pattern for access by the processor for processing the data, and that the memory means is responsive to read address signals for conveying to the interface device data received from the processor.
According to a third aspect of the present invention, an input/output device for a network element in which forms a part of a synchronous transmission system, comprising an interface device capable of transmitting a multiplex signal and processing a received multiplex signal, and a signal processing device for processing data received from the interface device, is characterized in that the signal processing device includes memory means for storing the data and a processor, that the memory means arrange the data in a predetermined pattern so that the processor can access and process the data, and that the memory means can convey to the interface device data received from the processor.
In further accord with these various aspects of the invention, they may be further characterized in that the memory means is for storing the data received from the interface device and from the programmable processor, in such a way that the data are arranged in groups containing data of a respective same type. The synchronous transmission is further characterized in that said access by the processor is for access to each of the groups as a block, wherein block size is variable. The synchronous transmission system is further characterized in that the processor is for rearranging a chronological order of the blocks and for storing the blocks in an internal memory. In still further accord with the first aspect of the present invention, the processor uses a transfer list for accessing the data arranged in groups, wherein the transfer list contains information for transferring data from a data source to a data sink, and that the processor is for recalculating the transfer list each time when the block size changes.
With the present invention, the network elements can advantageously be flexibly adapted to (ITU-T/ETSI) standards while these standards are still under development, with
Beisel Werner
Kasper Jürgen
Krips Wolfgang
Scheer David
Alcatel
Ton Dang
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