Network controller which enables the local processor to have gre

Details Network controller which enables the local processor to have gre Network controller which enables the local processor to have gre

1994-09-26

1998-06-09

Lee, Thomas C.

39520045, 39520059, 395882, 395836, G06F 1300

Patent

active

057650276

ABSTRACT:
An application specific integrated circuit (ASIC)/field programmable gate array (FPGA) which is a component of a wireless LAN controller including a local processor and a memory enables the controller to interface with both PCMCIA.TM. and AT.TM. host computer systems. The ASIC/FPGA enables communication between a radio frequency communication module, a local processor, and the host computer. The ASIC/FPGA also includes a throttle feature that decreases the access of the host computer in comparison to access of the local processor in order to enable the local processor to rapidly generate an acknowledge signal as required by various RF LAN specifications. During operation of the controller, data to be transmitted by the host computer onto the network is written by the host to an SRAM via the ASIC/FPGA, and the host commands the local processor via the ASIC/FPGA to forward the transmitted data to the RF communication module. Under the control of the ASIC/FPGA, the local processor then forwards the transmit data from the SRAM to the RF communication module. When data is received from the RF communication module, the local processor, under the control of the ASIC/FPGA, receives the data and stores the received data in the SRAM. The received data is then forwarded to the host computer via the ASIC/FPGA.

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