Network channel receiver architecture

Details Network channel receiver architecture Network channel receiver architecture

2000-06-13

2004-06-08

Olms, Douglas (Department: 2661)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S503000, C370S506000, C713S500000, C375S372000

Reexamination Certificate

active

06747997

ABSTRACT:

BACKGROUND
1. Field of the Invention
This invention relates generally to the transfer of data over a network. In particular, the present invention relates to the architecture of a network interface controller for a channel-based, switched fabric network.
2. Description of the Related Art
It has been suggested that some networks would benefit from having a channel oriented, switched fabric, serial link architecture designed to meet the growing needs of I/O reliability, scalability and performance on commercial high-volume servers. Next Generation I/O and Infiniband networks use an efficient engine that is coupled to host memory to replace shared buses with a fabric of switchable point-to-point links. This approach decouples the CPU from the I/O subsystem and addresses the problems of reliability, scalability, modular packaging, performance and complexity. Communication between CPU and peripherals occurs asynchronously with the I/O channel engine. The I/O channel engine is utilized to transport data to and from main memory and allow the system bus to act as a switch with point-to-point links capable of near linear scaling with CPU, memory and peripheral performance improvements.
One challenge to implementing a computer network which utilizes an channel oriented, switched fabric, serial link architecture is to ensure that the high-speed data communications between a data transmitter (source node) and a data receiver (destination node) operating in two different clocks are synchronous with respect to the transmission and reception of data within each data packet. Such data transmitter and data receiver may correspond to different nodes (end stations such as host computers, servers, and/or I/O devices) of a computer network which operate in synchrony with different clock signals. Failure to maintain synchronization between the data transmitter and data receiver may result in mis-communication (data corruption) and the effective loss of data. Therefore, a data receiver, such as a network interface controller or channel adapter, connected to such a network must transition the data stream from the network clock domain into its own core clock domain.
A block diagram depicting the connection of a network interface controller to receive data from a network communication link is shown in FIG.
1
. The serializer/deserializer (SERDES) attached to the network link generates a clock (RXCLK) in conjunction with the link data (RXD). Due to instability in the RXCLK clock signal, it is desirable to reduce the amount of logic in the RXCLK domain. It is also desirable that a host processing system be informed whenever something catastrophic happens on the serial interface. A malfunctioning or disconnected SERDES in the serial interface constitutes a catastrophic event. Therefore, the network interface controller should be capable of detecting these types of events across asynchronous clock domains and informing the host processing system.


REFERENCES:
patent: 6055285 (2000-04-01), Alston
patent: 6289066 (2001-09-01), LaVigne et al.
patent: 6425034 (2002-07-01), Steinmetz et al.

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